Coherence apparatus for cache of multiprocessor

A cache coherence apparatus comprising:

• a plurality of processor groups each consisting of a plurality of processors;
• a main storage which is shared for said processor groups;
• a cache unit, provided for every said plurality of processors, for performing an access of said main storage;
• a directory memory for storing a registration state data of said main storage into said cache units on a cache line unit basis;
• an internal common bus for connecting said main storage and said cache units;
• an external common bus for connecting said plurality of processor groups;
• and
• a memory control module for controlling in the case where access data is not registered in any one of said plurality of cache units for access requests of said plurality of processors, said directory memory is accessed, and when the access data is not registered, said main storage is accessed and a response is issued, and when the access data has been registered, the cache unit of a registration destination is accessed and a response is issued, and after completion of the response of said access data, the registration state in said directory memory is updated.

A cache coherence apparatus comprising:

• an external common bus;
• and
• a plurality of processor groups coupled to said external common bus comprising:
• an internal common bus,
• a plurality of processors coupled via said internal bus,
• a cache memory coupled to each of said plurality of processors and coupled to said internal common bus,
• a main storage memory;
• and
• a memory control module coupled to said main storage memory, said external common bus, and said internal common bus, and receiving a data read request from any one of said plurality of processors, and if said data is not contained in said processor group, transmitting an access command via said external common bus to another processor group which contains said data, a memory control module of said another processor group retrieving and transmitting said data to said memory control module which transmitting said access command over said external common bus;
• wherein
• said memory control module monitors said external common bus for said data, retrieves said data from said external common bus upon detection thereof and updates the cache memory of the requesting processor and the main storage memory in said data read request.

A computer apparatus comprising:

• a plurality of processor modules interconnected by an external common bus, each processor module having a plurality of processors interconnected by an internal common bus, each processor having a cache and each processor module having a memory control module to control how read requests are handled by the processor module and to monitor traffic on the external bus relating to read requests;
• a main storage distributed amongst the processor modules in respective distributed parts of main storage, wherein each of said plurality of processor modules has a directory memory for storing on a cache line basis a registration state for the corresponding data stored in the distributed part of main storage of the processor module concerned;
• said memory control module identifying by reference to the directory memory of the processor module concerned whether the newest value of the requested data is stored in a cache of the processor module concerned and, if so, responding to such a read request by placing the newest value of that data on the external common bus for the requesting processor module;
• and
• said memory control module identifying whether data placed on the external common bus in response to a read request relates to an address in the distributed part of main storage in the processor module concerned and if said address relates to said distributed part of main storage retrieving said data from the external common bus and updating the data in the corresponding address in the distributed part of main storage, thereby maintaining cache coherence by performing copy-back as a result of read requests.