Concurrent write of multiple chunks of data into multiple subarrays of flash EEPROM

An EEPROM chip comprising:

• a plurality of EEPROM subarrays, and
• a circuit for concurrently writing data into selected memory locations of said plurality of EEPROM subarrays, said circuit including,
• a plurality of address latches,
• a plurality of data registers individually coupled to a corresponding one of said plurality of EEPROM subarrays,
• means for storing subarray addresses into selected ones of said plurality of address latches, wherein individual ones of said plurality of subarray addresses are coded such that a first plurality of bits indicates the subarray in which the subarray location indicated by said subarray address resides, a second plurality of bits indicates a row address and a third plurality of bits indicates a column address of the subarray indicated by said first plurality of bits, and for storing data to be written into subarray locations indicated by said subarray addresses, into selected ones of said plurality of data register, wherein said storing means includes means for decoding said first plurality of bits to generate a signal to enable the data register coupled to the subarray indicated by said first plurality of bits,
• said plurality of address latches including a plurality of row address latches and a plurality of column address latches for respectively latching said row addresses indicated by said second plurality of bits and said column addresses indicated by said third plurality of bits,
• wherein said storing means additionally includes means for generating a plurality of signals to enable the pluralities of row and column address latches for storing said row and column addresses indicated by said second and third plurality of bits, and
• means for concurrently writing said data stored in said plurality of data registers into the subarray locations indicated by said subarray addresses stored in said plurality of address latches.

A method of concurrently writing a plurality of data chunks into an EEPROM, comprising the steps of:

• sequentially storing said plurality of data chunks into a plurality of data storage means respectively coupled to corresponding subarrays of said EEPROM, including the steps of:
• sequentially receiving a plurality of subarray addresses indicative of subarray locations wherein corresponding data chunks of said plurality of data chunks are to be written;
• and
• sequentially storing said corresponding data chunks into said plurality of data storage means such that individual ones of said corresponding data chunks are stored in the data storage means coupled to the subarray including the subarray location indicated by the subarray address corresponding to said individual one data chunk;
• providing row and column select signals to row and column decoder means coupled to said corresponding subarrays of said EEPROM;
• and
• concurrently writing said plurality of data chunks stored in said plurality of data storage means into subarray locations of said corresponding subarrays of said EEPROM as indicated by said row and column select signals.