Symmetric multiprocessing computer with non-uniform memory access architecture

A scalable distributed memory multiprocessor computer system including a backplane comprising a plurality of identical independent backplane buses, said backplane providing communication paths for a plurality of motherboards, each of said motherboards including at least one processor with a local cache memory, a motherboard communications bus, a motherboard communications bus to backplane interface module, and a memory system, wherein:

• said motherboard communications bus to backplane interface module includes three input queues of high, medium, and low priority, and packets sent on said backplane to a motherboard are placed in one of said input queues depending on the priority of each packet;
• all packets to the same cache line use the same one of said plurality of identical independent backplane buses;
• high priority packets are always accepted into said memory system on a motherboard without needing to retry;
• medium priority packets received from said plurality of identical independent backplane buses are granted onto a motherboard communication bus in the order in which said medium priority packages are received from said plurality of identical independent backplane buses;
• packets for cache-inhibited reads, cache-inhibited writes, and cache-inhibited write unlocks are ordered with previous invalidate command and read invalidate reply packets previously inserted in said medium priority input queue;
• packets to be received by more than one motherboard will arrive to each motherboard simultaneously;
• all copyback invalidate commands and copyback commands are sent out on said backplane to a receiving motherboard;
• all invalidate copybacks are sent out on said backplane to a receiving motherboard;
• and
• a motherboard will retry any local resource requests while said medium input queue of said motherboard communications bus to backplane interface module contains any read invalidate reply, invalidate command, or copyback invalidate command packets.

A scalable multiprocessor computer system, comprising:

• a backplane, including at least one backplane communication bus;
• a plurality of motherboards, detachably connected to said backplane;
• each motherboard interfacing to said at least one backplane communication bus, each of said plurality of motherboards including:
• at least one backplane communication bus interface mechanism interfacing at least one of said plurality of motherboards to said at least one backplane communication bus;
• a motherboard communication bus comprising a first segment that is selectably interfaceable to said at least one backplane communication bus and a plurality of second segments, said motherboard communication bus including means for selectably interconnecting one of said plurality of second segments of said motherboard communication bus to said first segment;
• an arbitration means for arbitrating requests from said plurality of motherboards for access to said first segment and said one of said plurality of second segments of said motherboard communication bus by selected ones of said plurality of motherboards;
• a memory system including main memory distributed among said plurality of motherboards, directory means for maintaining main memory coherency with caches on other motherboards, and a memory controller means for accessing said main memory and directory memory and interfacing to said motherboard communication bus;
• and
• at least one daughterboard, detachably connected to said motherboard and interfacing to said motherboard communication bus, said at least one daughterboard further including:
• a motherboard communication bus interface means for interfacing said at least one daughterboard to said motherboard communication bus and a local bus on said daughterboard;
• and
• at least one cache memory system including cache memory and a cache controller means for maintaining said cache memory for a processor of said scalable multiprocessor computer system.

A crossbar register switch for use in a scaleable multiprocessor computer system including at least one backplane communication bus, and a plurality of motherboards interfaced to said at least one backplane communication bus, each of said plurality of motherboards including a motherboard communication bus comprising a first segment that is selectably interfaceable to said at least one backplane communication bus and a plurality of second segments;

• said crossbar register switch comprising:
• an interface to said first segment of said motherboard communication bus;
• a plurality of bidirectional ports, said bidirectional ports interfacing to said plurality of second segments of said motherboard communication bus;
• a motherboard communication bus request arbitration mechanism arbitrating requests from said plurality of motherboards for access to said first segment and to one of said plurality of second segments of said motherboard communication bus by selected ones of said plurality of motherboards;
• wherein said crossbar register switch selectably interconnects said first segment of said motherboard communication bus to one of said second segments of said motherboard communication bus through a bidirectional port based arbitration by said motherboard communication bus request arbitration mechanism.

In a scalable distributed memory multiprocessor computer system including a backplane comprising a plurality of identical independent backplane buses, said backplane providing communication paths for a plurality of motherboards, each of said motherboards including at least one processor with a local cache memory, a motherboard communications bus, a motherboard communications bus to backplane interface module, and a memory system;

• a method for communicating between said motherboard communication bus and said backplane busses comprising:
• providing three input queues of high, medium, and low priority;
• designating which input queue to place a packet sent on said backplane to a motherboard;
• guaranteeing that high priority packets will be received at the destination;
• allowing packets to be received by more than one motherboard to arrive to each motherboard simultaneously;
• ordering packets in said medium priority queue so that any medium priority packets which involve snoops or invalidations are ordered with previous invalidate command and read invalidate reply packets previously inserted in said medium priority queue across all backplane busses;
• and
• sending any local memory requests out onto one of said backplane busses and into said while said medium priority queue of said motherboard communications bus to backplane interface module contains any read invalidate reply, invalidate command, or copyback invalidate command packets.