Differential decoder circuit
AssigneeNEC Corporation
InventorJunichi Ishigami
Life of this patent
Estimating the term…
Abstract
Disclosed is a differential decoder circuit, which has: a pair of first and second transistors which form a differential connection, wherein a base of the first transistor is supplied with a reference bias voltage and a base of the second transistor is supplied with an input signal to be decoded to thereby output a decode output depending on the input signal from collector outputs of the first and second transistors; a constant-voltage source; a first bias means for supplying a bias voltage determined by a constant voltage of the constant-voltage source with the base of the first transistor; and a second bias means for supplying the alternative of a voltage determined by the input signal and the voltage determined by the constant voltage depending on a level of the input signal with the base of the second transistor.
Claims6
A differential decoder circuit, comprising:
- a pair of first and second transistors which form a differential connection, wherein a base of said first transistor is supplied with a reference bias voltage and a base of said second transistor is supplied with an input signal to be decoded to thereby output a decode output depending on said input signal from collector outputs of said first and second transistors;
- a constant-voltage source;
- a first bias means for supplying a bias voltage determined by a constant voltage of said constant-voltage source with said base of said first transistor;
- and
- a second bias means for supplying the alternative of a voltage determined by said input signal and said voltage determined by said constant voltage depending on a level of said input signal with said base of said second transistor.
A differential decoder circuit, comprising:
- a plurality of n-stage differential circuits which are longitudinally connected, wherein n is two or more, and include a pair of first and second transistors, respectively, which form a differential connection, respective bases of said first transistor being supplied with a predetermined reference bias voltage, wherein a base of said second transistor of each of said n-stage differential circuits is supplied with an input signal to be decoded to thereby output a decode output depending on said input signal from collector outputs of said first and second transistors of stage number n;
- a constant-voltage source;
- a first bias means for supplying a bias voltage determined by a constant voltage of said constant-voltage source with said base of said first transistor of each of said n-stage differential circuits;
- and
- a second bias means for supplying the alternative of a voltage determined by said input signal and said voltage determined by said constant voltage depending on a level of said input signal with said base of said second transistor of each of said n-stage differential circuits.
Dependencies are inferred from the claim text.