US 5,886,582 A · Enabling clock signals with a phase locked loop (PLL) lock detect circuit

Abstract

A circuit for enabling and disabling generation of an output clock signal is disclosed. The circuit includes a PLL lock detect circuit that generates an active lock control signal when an output reference signal of a phase lock loop (PLL) circuit is phase locked relative to an input reference signal to the PLL. The output reference signal of the PLL, and the lock signal from the lock detect circuit, are both provided to a clock enable circuit. The clock enable circuit includes a negative edge-triggered D-type flip-flop and a two-input AND gate. The lock signal is applied to the D-input of the flip-flop, while the clock signal is applied to the clock input of the flip-flop. The lock signal is generated asynchronously relative to the input clock signal. Therefore, the flip-flop samples the lock signal on each falling edge of the clock signal so as to synchronize the lock signal relative to the input clock signal. The sampled lock signal, and the input clock signal (formed from the PLL output reference signal) are provided on respective input terminals of the AND gate. The output of the AND gate defines the output clock signal.

Claims22

Dependent claims

A method of operating a clock signal generator comprising the step of:

generating a lock signal in response to (i) a window signal and (ii) one or more control signals;
and
generating an output clock signal in response to (i) an input clock signal and (ii) said lock signal, wherein said lock signal corresponds to a lock state of a phase locked loop (PLL).

Dependencies are inferred from the claim text.

Enabling clock signals with a phase locked loop (PLL) lock detect circuit

Life of this patent

Enabling clock signals with a phase locked loop (PLL) lock detect circuit

Life of this patent

Abstract

Claims22