US 5,884,027 A · Architecture for an I/O processor that integrates a PCI to PCI bridge

Abstract

A multi-functional device that integrates a high performance processor into a PCI to PCI bus bridge. The invention consolidates a high performance processor, a PCI to PCI bus bridge, PCI bus-processor address translation unit, direct memory acces's (DMA) controller, memory controller, secondary PCI bus arbitration unit, inter-integrated circuit (I.sup.2 C) bus interface unit, advanced programmable interrupt (APIC) bus interface unit, and a messaging unit into a single system which utilizes a local memory. The PCI bus is an industry standard high performance, low latency system bus. The PCI to PCI bridge provides a connection path between two independent 32-bit PCI buses and provides the ability to overcome PCI electrical loading limits. The addition of the local processor brings intelligence to the PCI bus bridge.

Claims26

Dependent claims

An integrated circuit for coupling a first PCI external bus to a second PCI external bus comprising:

a) a first internal bus for coupling to said first PCI external bus;
b) a second internal bus for coupling to said second PCI external bus;
c) a PCI-PCI bus bridge having a first bus interface coupled to said first internal bus and a second bus interface coupled to said second internal bus, said bus bridge for allowing transactions to be passed between said first and second external PCI buses;
d) a local processor having a local address space, said local processor coupled to said bus bridge for processing transactions received from external sources and transactions input to said first bus interface and said second bus interface;
e) a local bus for passing data between said processor and a memory accessible within said local address space,
f) a memory controller for controlling writes to and reads from said memory using data and addresses on said local bus.

3 more elements

A system including at least one host processor coupled to a primary PCI bus and at least one peripheral device coupled to a secondary PCI bus comprising in a single integrated circuit:

a) a first internal bus coupled to said primary PCI bus;
b) a second internal bus coupled to said secondary PCI bus;
c a bus bridge having a first bus interface coupled to said first internal bus and a second bus interface coupled to said second internal bus, said bus bridge for allowing transactions to be passed between said primary PCI bus and said secondary PCI bus;
d local processor coupled to said bus bridge for processing transactions received from external sources and transactions input to said first bus interface and said second bus interface;
e a local bus for passing data between said processor and a memory;
f) a memory controller for controlling writes to and reads from said memory using data and addresses on said local bus.

3 more elements

Dependencies are inferred from the claim text.

Architecture for an I/O processor that integrates a PCI to PCI bridge

Life of this patent

Architecture for an I/O processor that integrates a PCI to PCI bridge

Life of this patent

Abstract

Claims26