Method and apparatus for reading/writing data in a memory system including programmable resistors

A semiconductor memory device comprising:

• a semiconductor substrate;
• a matrix array of memory cells arranged in plural rows and columns on said substrate, each memory cell including a resistor programmable to one of a first resistance state and a second resistance state;
• a plurality of column lines respectively coupled to the plural columns of memory cells;
• a plurality of row lines respectively coupled to the plural rows of memory cells;
• a column decoder circuit connected to select one of said column lines;
• a row decoder circuit connected to select one of said row lines;
• a column output line coupled to each of said column lines;
• a reference line coupled to a fixed resistance element;
• and
• a comparator circuit coupled to said column output line and said reference line, said comparator circuit comparing a sense current flowing through said column output line and a selected programmable resistor coupled to said selected one of said row lines and a reference current flowing through said reference line and said fixed resistance element to thereby output a signal indicative of a resistance state of said programmable resistance element.

A semiconductor memory device comprising:

• a semiconductor substrate;
• an array of programmable resistance elements formed on said substrate, each including a resistor programmable to one of a first resistance value and a second resistance value, said programmable resistance elements arranged in a plurality of rows and columns;
• a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in each of said columns;
• a plurality of row lines respectively coupled to pluralities of programmable resistance elements arranged in each of said rows;
• a column decoder circuit connected to select one of said column lines;
• a row decoder circuit connected to select one of said row lines;
• a column output line coupled to each of said column lines;
• a write circuit coupled to said column output line to supply one of a first write voltage and a second write voltage to one of said programmable resistors coupled to said selected column line and said selected row line, said first write voltage programming said programmable resistor to said first resistance state and said second write voltage programming said programmable resistor to said second resistance state.

A semiconductor memory device comprising:

• an array of programmable resistance elements, each including a resistor programmable to one of a first resistance value and a second resistance value, said programmable resistance elements arranged in a plurality of rows and columns;
• a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in each of said columns;
• a column output line coupled to each of said column lines;
• and
• a shunt protection circuit coupled to limit a current flowing through said column output line and said column lines.

A method of operating a memory, said memory including an array of programmable resistance elements, each programmable to one of a first resistance value and a second resistance value, said programmable resistance elements arranged in pluralities of rows and columns;

• a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in said columns;
• a plurality of row lines respectively coupled to pluralities of programmable resistance elements arranged in said rows;
• a column decoder circuit connected to select one of said column lines;
• and a row decoder circuit connected to select one of said row lines, said method comprising the steps of:
• driving one of said plurality of column lines to a first potential in accordance with an output of said column decoder;
• driving one of said plurality of row lines to a second potential in accordance with an output of said row decoder;
• directing a sense current though a programmable resistance element coupled to said one of said plurality of column lines and said one of said plurality of row lines;
• and
• comparing said sense current with a reference current, to determine a programmed resistance of said programmable resistance element.

A method of operating a memory, said memory including an array of programmable resistance elements, each programmable to one of a first resistance value and a second resistance value, said programmable resistance elements arranged in a plurality of columns;

• a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in each of said columns, said method comprising the steps of:
• supplying a current to one of said column lines;
• and
• coupling a shunt circuit to said column lines to limit said current to not exceed a predetermined magnitude.

A semiconductor memory device comprising:

• an array of programmable resistance elements, each including a resistor comprising chalcogenide material and being programmable to one of a first resistance value and a second resistance value, said programmable resistance elements arranged in a plurality of rows and columns;
• a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in each of said columns;
• a column output line coupled each of said column lines;
• and
• a shunt protection circuit limiting a current flowing through said column output line and said column lines.

A semiconductor memory device comprising:

• an array of programmable resistance elements, each including a resistor programmable to one of a first resistance value and a second resistance value, said programmable resistance elements arranged in a plurality of rows and columns;
• a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in each of said columns;
• a column output line coupled to each of said column lines;
• and
• a shunt protection circuit coupled to limit voltages appearing on said column output line and said column lines.

A method of operating a memory, said memory including an array of programmable resistance elements, each programmable to one of a first resistance value and a second resistance value, said programmable resistance elements arranged in a plurality of columns;

• a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in each of said columns, said method comprising the steps of:
• supplying a current to one of said column lines;
• and
• coupling a shunt circuit to said column lines to limit a voltage on said one of said column lines to not exceed a predetermined magnitude.