US 5,883,814 AGranted

System-on-chip layout compilation

AssigneeInternational Business Machines Corporation

InventorsWing K. Luk, Wei Hwang, Yasunao Katayama

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Abstract

A layout compiler compiles from hardware description language (HDL) and schematic description of a design, which consists of dynamic random access memory (DRAM) components and logic components, to the layout of an integrated logic and DRAM system on a single integrated chip. The layout compiler creates the physical structure (floor-plan) of integrated logic/DRAM chips and generates on-chip interconnections between the DRAM components and logic components. By integrating logic and DRAM memory onto the same chip, the performance gap which is the difference between the logic processor's data processing rate and the DRAM memory's data access rate can be minimized. Further, the bandwidth between the logic processor and the DRAM memory can be increased significantly. The layout methods eliminate the off-chip drivers and heavy capacitive loads presented in the off-chip interconnections. Low power dissipation is a direct result of integrated logic/DRAM chip in high frequency operations. This method enables the optimization of the on-chip metal interconnections between the logic components and the DRAM components in a way to achieve higher system bandwidth and system performance, lower power dissipation and packaging cost.

Claims11

Dependent claims

A computer implemented method of compiling a layout of a system on a single integrated circuit chip, said system including a microprocessor core and system logic and dynamic random access memory (DRAM) organized in blocks, the method comprising the steps of:

extracting from a hardware description database information on various functional units and generating a macro placement and floor plan of the chip;
configuring and compiling a DRAM memory component of the chip into DRAM macros;
generating an overall physical layout structure for DRAM macros and logic macros;
generating an overall chip power distribution structure and grid for DRAM macros and logic macros including power distribution grid internal to the logic macros;
generating chip level interconnections of all DRAM, logic and chip supporting macros according to a chip level net list specification stored in a data base;
implementing a global structure of the chip based on the generated overall physical layout structure, the generated overall chip power distribution structure and the generated chip level interconnections;
generating logic macros using logic synthesis followed by placement and wiring of books of transistors according to the generated chip image;
performing clock and timing verification, design rule checking and logic simulation to verify design correctness;
generating a chip layout by wiring interconnections between all macros and adding decoupling elements and checking again for design rule correctness and timing;
and
outputting final chip layout for fabrication processing.

8 more elements

A computer based design system for compiling a layout of a system-on-chip design including a microprocessor core and system logic and dynamic random access memory (DRAM) organized in blocks, the design system comprising:

a source of system specifications for a DRAM memory subsystem, a microprocessor core, a cache, a system control bus, and input/output (I/O) for the system-on-chip design;
a DRAM configurator receiving the specifications for the DRAM memory subsystem and generating an overall physical layout structure for DRAM macros including a power distribution network for the DRAM macros;
a bus and interface synthesizer receiving the specifications for the system bus and I/O and synthesizing logic necessary to connect various logic and DRAM macros on the chip;
a logic synthesizer receiving an output from the bus and interface synthesizer and the specifications for the microprocessor core and cache and generating logic macros and wiring of books of transistors according to a generated chip image including a power distribution network for the logic macros separate from the power distribution network for the DRAM macros to minimize noise coupling between DRAM and logic macros;
and
a chip integration function receiving outputs of the DRAM configurator, bus and interface synthesizer and logic synthesizer and generating a chip layout by wiring interconnections between all macros and adding decoupling elements, and a layout extraction function performing clock and timing verification, design rule checking and logic simulation to verify design correctness.

3 more elements

Dependencies are inferred from the claim text.