Synchronous semiconductor memory device in which current consumed by input buffer circuit is reduced

A synchronous semiconductor memory device operating in synchronization with an externally applied external clock signal, comprising:

• clock buffer means for generating a first internal clock signal in accordance with said external clock signal;
• latch means for taking in an externally applied external clock enable signal designating validity of said external clock signal in synchronization with said first internal clock signal, and for generating and outputting an input buffer enable signal which is activated when said external clock enable signal is active;
• clock enable means for delaying said input buffer enable signal for generating an internal clock enable signal;
• internal clock generating means activated in response to said internal clock enable signal being active, for generating a second internal clock signal in accordance with said external clock signal;
• internal signal generating means for latching a received signal in synchronization with said second internal clock signal for generating an internal signal.

A synchronous semiconductor memory device operating in synchronization with an externally applied external clock signal, comprising:

• clock buffer circuitry for generating a first internal clock signal in accordance with said external clock signal;
• a buffer circuit for buffering an externally applied external clock enable signal designating validity of said first internal clock signal;
• a first latch coupled to receive an output signal from said buffer circuit, set to a through state permitting passage of the output signal from said buffer circuit in response to said first internal clock signal being at a first potential level and set to a latch state for maintaining an output signal thereof regardless of the state of the output signal from said buffer circuit in response to said first internal clock signal being at a second potential level;
• a second latch coupled to said first latch, set to said latch state in response to said first internal clock signal being at said first potential level and set to said through state in response to said first internal clock signal being at said second potential level, for generating and outputting an input buffer enable signal which is activated when said external clock enable signal is active;
• a latch circuit coupled to said second latch and set to the latch state complementarily to said second latch in synchronization with said first internal clock signal, for delaying said input buffer enable signal to generate an internal clock enable signal;
• internal clock generating circuitry activated in response to said internal clock enable signal being active, for generating a second internal clock signal in accordance with said external clock signal;
• and
• an input buffer means for buffering an externally applied signal different from said external clock enable signal and said external clock signal to generate a pre-internal signal when activated in response to said input buffer enable signal being active, said input buffer means including means for shutting off a current flowing through the input buffer means to inactivate the buffering operation in response to said input buffer enable signal being inactive.