Surface mount multilayer capacitor

An electrical circuit arrangement comprising:

• a generally planar circuit board having a plurality of electrical current paths defined thereon;
• and
• a capacitor device having a capacitor body surface-mounted on said circuit board and having at least four electrical terminals thereon, said terminals being in respective electrical communication with predetermined ones of said current paths, said capacitor body including:
• (a) at least one first electrode plate having a generally rectangular first main electrode portion with a plurality of first lead structures extending therefrom;
• (b) at least one second electrode plate situated in opposed and spaced apart relation to said first electrode plate, said second electrode plate having a generally rectangular second main electrode portion with a plurality of second lead structures extending therefrom;
• (c) said electrode plates being situated in a plane substantially parallel to a plane of said circuit board;
• (d) respective ones of said first lead structures being located adjacent respective ones of said second lead structures in an interdigitated arrangement and extending to respective ones of said electrical terminals;
• and
• (e) a ceramic material located between each opposing set of said first and second electrode plates to provide a predetermined dielectric constant.

A multilayer ceramic capacitor comprising:

• a low-aspect capacitor body having a unitary structure characteristic of a plurality of stacked, pressed and sintered ceramic-electrode layers;
• said capacitor body including a plurality of first polarity electrical terminals and a plurality of second polarity electrical terminals located on the outer surface thereof, said plurality of electrical terminals being formed by a thick-film terminal material;
• each ceramic-electrode layer including an electrode plate having a main electrode portion with a plurality of lead structures extending therefrom, said electrode plates being interleaved such that 15 respective lead structures of first alternating electrode plates are electrically connected to respective first polarity terminals and respective lead structures of second alternating electrode plates are electrically connected to respective second polarity terminals;
• and
• wherein said capacitor is constructed and arranged to exhibit an inductance of less than approximately 100 picohenries.

A capacitor array having a plurality of capacitor devices in a surface mount compatible package, said array comprising:

• a capacitor body having a unitary structure characteristic of a plurality of stacked, pressed and sintered ceramic-electrode layers, said ceramic electrode layers comprising a plurality of first ceramic-electrode layers and a plurality of second ceramic-electrode layers;
• said capacitor body including a plurality of first polarity electrical terminals and a plurality of second polarity electrical terminals located on the outer surface thereof;
• said first ceramic-electrode layers including an electrode plate having a first main electrode portion with a plurality of first lead structures extending therefrom;
• said second ceramic-electrode layers including at least four coplanar second electrode plates situated in opposed and spaced apart relation to said first electrode plate, said second electrode plates each having a second main electrode portion with at least one second lead structure extending therefrom;
• respective ones of said first lead structures being located adjacent respective ones of said second lead structures in an interdigitated arrangement and extending to respective ones of said electrical terminals;
• wherein said capacitor array has a number of capacitor devices equal to a number of said second electrode plates.