Method for fabricating an array of ultra-small pores for chalcogenide memory cells

A method of fabricating an array of chalcogenide memory cells, comprising the steps of:

• applying a first layer of dielectric material onto a substrate that includes an array of conductive regions;
• removing a portion of said first layer of said dielectric material to define an upper surface with generally vertical surfaces extending therefrom to a lower surface in said first layer of said dielectric material, said upper surface being generally horizontal and including a horizontal surface that is generally cross shaped;
• applying a fixed layer of a second material onto said generally vertical surfaces of said first layer of said dielectric material, said fixed layer of said second material having a first thickness;
• applying a second layer of said dielectric material onto said fixed layer of said second material;
• removing said fixed layer of said second material to define an array of pores in said dielectric material layers, said array of pores generally vertically aligned with said array of conductive regions of said substrate;
• and
• providing a chalcogenide memory cell at each of said pores by the steps comprising:
• applying a layer of chalcogenide material onto a region of said dielectric material layer generally centered at said pore, said layer of chalcogenide material extending into said pore;
• and
• applying a layer of conductive material onto said chalcogenide layer.