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US 5,879,787 AGranted
Method and apparatus for improving wireability in chip modules
AssigneeW. L. Gore & Associates, Inc.
InventorWilliam George Petefish
Life of this patent
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Abstract
A method of making a laminated structure includes forming a first lamination having first and second conductive layers having inner and outer surfaces and being spaced apart by a dielectric layer, drilling through the first conductive layer and dielectric layer to form a blind via having a bottom coexistent with the inner surface of the second conductive layer, plating the blind via with a conductive material, and patterning the second conductive layer to form at least one contact pad over the blind via.
Claims2
A laminated structure comprising:
- a first lamination having first and second conductive layers having inner and outer surfaces and being spaced apart by a dielectric layer, wherein the dielectric layer is an expanded polytetrafluoroethylene (PTFE) matrix impregnated with cyanate ester and epoxy;
- at least one blind via formed through the first conductive layer and dielectric layer and having a bottom coexistent with the inner surface of the second conductive layer;
- a conductive material plated into the blind via;
- and
- a contact pad patterned from the second conductive layer and disposed over the blind via, said contact pad having a single planar surface.
2 more elements
Dependencies are inferred from the claim text.