HDLC integrated circuit using internal arbitration to prioritize access to a shared internal bus amongst a plurality of devices

A high level data link control (HDLC) integrated circuit of a type including at least one HDLC controller and one direct memory access (DMA) controller, the HDLC circuit including organizing means for organizing access to a first external bus for connection to an external memory via an internal bus to which are connected a plurality of different entities which require access to the external memory, said DMA controller being one of said entities and the internal bus being connected to the first external bus via a memory controller integrated in the HDLC circuit and constituting an electric interface between the internal bus and the first external bus,

• wherein the organizing means comprises an arbitration device receiving a plurality of asynchronous access request signals representing requests for access to the internal bus issued by each entity of said plurality of entities, respectively, the arbitration device issuing a plurality of binary signals authorizing access to one of said entities, respectively, based on a determination of priority between the different access requests by a wired logic priority decoder associated with an input register, a loading of a state of the access request signals in the input register happening, if no memory cycle is running, periodically, by a clock signal and, if a memory cycle is running, at an occurrence of a pulse on a signal issued by the memory controller anticipating an end of the memory cycle by a processing delay which is a function of a processing time of the plurality of access requests performed by the priority decoder.

A high level data link control (HDLC) integrated circuit, comprising:

• a first external bus;
• an internal bus;
• a memory controller integrated in the HDLC circuit which connects the first external bus to the internal bus;
• a plurality of different entities connected to the internal bus, each different entity requiring access to the external memory at some time during its operation;
• and
• prioritizing means, connected to the memory controller and each different entity, for prioritizing, among the plurality of different entities, access to the first external bus, wherein the prioritizing means comprises:
• an input register to receive at least one asynchronous binary signal of a first type representing a request for access to the internal bus issued by at least one entity of said plurality of entities;
• an output register;
• and
• a wired logic priority decoder connected to the input register and to the output register, the priority decoder issuing at least one binary signal of a second type to authorize the access of the at least one requesting entity to the internal bus based on a determination of priority among different access requests.

A high-level data link control (HDLC) circuit for controlling access to an external bus among a plurality of devices, the HDLC circuit comprising:

• an internal bus;
• a first external bus;
• a plurality of devices connected to the internal bus, each of the devices to read/write data from/to the internal bus;
• a memory controller connected to the internal bus and the first external bus, the memory controller to transfer address and data information between the internal bus and the first external bus;
• and
• an arbitration device connected to each access device of the plurality of access devices and the memory controller, the arbitration device to receive at least one request to access the first external bus through the internal bus from at least one access device and the arbitration device to grant access to a requesting access device having a highest access priority level amongst the access devices requesting access by sending an access granted signal to the requesting access device having the highest access priority level amongst the access devices requesting access,
• wherein the arbitration device comprises:
• an input register to receive the at least one access request from the at least one access device:
• a priority register to store a plurality of unique access priority levels associated, respectively, with each access device of the plurality of access devices:
• a priority decoder circuit connected to the priority register and the input register, the priority decoder circuit to receive the at least one access request from the input register and determine an access priority level for each at least one access request as a function of the access priority levels stored in the priority register, the priority decoder circuit to output the access granted signal to the requesting access device having the highest access priority level;
• and
• an output register connected to the plurality of access devices the output register to receive the access granted signal from the priority decoder circuit and output the access granted signal to the requesting access device having the highest access priority level.

A method of controlling access to an internal bus in a high level data link control circuit including the internal bus and a plurality of entities, wherein one entity of the plurality of entities is a memory refresh device, the plurality of entities connected to the internal bus, the method comprising the steps of:

• defining a refresh period as a maximum time interval allowable between two accesses of the internal bus made by the memory refresh device;
• assigning a unique access priority level to each entity of the plurality of entities other than the memory refresh device;
• assigning a lowest access priority level to the memory refresh device during a first part of the refresh period;
• receiving at least one access request to access the internal bus from at least one of the entities of the plurality of entities;
• and
• granting access to the requesting entity having the highest access priority level among the entities requesting access.