US 5,878,237 AGranted

Apparatus, method and system for a comuter CPU and memory to PCI bridge having a pluarlity of physical PCI buses

AssigneeCompaq Computer Corporation

InventorSompong P. Olarig

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Abstract

A core logic chip set in a computer system provides a bridge between processor host and memory buses and a plurality of peripheral component interconnect ("PCI") buses capable of operating at 66 MHz. Each of the plurality of PCI buses have the same logical bus number. The core logic chip set has an arbiter having Request ("REQ") and Grant ("GNT") signal lines for each PCI device connected to the plurality of PCI physical buses. Each of the plurality of PCI buses has its own read and write queues to provide transaction concurrency of PCI devices on different ones of the plurality of PCI buses when the transaction addresses are not the same or are M byte aligned. Upper and lower memory address range registers store upper and lower memory addresses associated with each PCI device. Whenever a transaction occurs, the transaction address is compared with the stored range of memory addresses. If a match between addresses is found then strong ordering is used. If no match is found then weak ordering may be used to improve transaction latency times. PCI device to PCI device transactions may occur without being starved by CPU host bus to PCI bus transactions.

Claims55

Dependent claims

A computer system having a core logic chip set capable of bridging between a processor host bus, memory bus and a plurality of peripheral component interconnect (PCI) buses wherein the plurality of PCI buses each have the same logical PCI bus number, said system comprising:

a central processing unit connected to a host bus;
a random access memory connected to a random access memory bus;
a core logic chip set connected to the host bus and the random access memory bus;
said core logic chip set configured as a first interface bridge between the host bus and the random access memory bus;
said core logic chip set configured as a plurality of second interface bridges between the host bus and a plurality of peripheral component interconnect (PCI) buses;
said core logic chip set configured as a plurality of third interface bridges between the memory bus and the plurality of PCI buses, wherein the plurality of PCI buses are physically separate but have the same logical PCI bus number;
a PCI address comparator;
a PCI arbiter for receiving request signals from and issuing grant signals to PCI devices connected to said plurality of PCI buses;
and
a PCI target flow controller;
said PCI address comparator receiving transaction addresses from said plurality of PCI bus interfaces, wherein the transaction addresses are compared and an address match is found if the transaction addresses from two or more of said plurality of PCI bus interfaces are the same or are within M bytes of each other, where M=16.times.2.sup.n and n is zero or a positive integer number, then said PCI address comparator sends an address match signal to said PCI target flow controller which causes a retry signal to be issued from the one of said plurality of PCI bus interfaces that corresponds to the newest transaction request causing the address match, if the transaction addresses from two or more of said plurality of PCI bus interfaces are not the same nor are the transaction addresses within M bytes then no address match signal is generated.

8 more elements

A method, in a computer system having a core logic chip set capable of bridging between a processor host bus, memory bus and a plurality of peripheral component interconnect (PCI) buses wherein the plurality of PCI buses each have the same logical PCI bus number, said method comprising the steps of:

providing a central processing unit connected to a host bus;
providing a random access memory connected to a random access memory bus;
providing a core logic chip set connected to the host bus and the random access memory bus;
configuring said core logic chip set as a first interface bridge between the host bus and the random access memory bus;
configuring said core logic chip set as a plurality of second interface bridges between the host bus and a plurality of peripheral component interconnect (PCI) buses, wherein the plurality of PCI buses are physically separate but have the same logical PCI bus number;
configuring said core logic chip set as a plurality of third interface bridges between the random access memory bus and the plurality of PCI buses;
providing a PCI address comparator;
providing a PCI arbiter for receiving request signals from and issuing grant signals to PCI devices connected to said plurality of PCI buses;
and
providing a PCI target flow controller;
said PCI address comparator receiving transaction addresses from said plurality of PCI bus interfaces, wherein the transaction addresses are compared and an address match is found if the transaction addresses from two or more of said plurality of PCI bus interfaces are the same or are within M bytes of each other, where M=16.times.2.sup.n and n is zero or a positive integer number, then said PCI address comparator sends an address match signal to said PCI target flow controller which causes a retry signal to be issued from the one of said plurality of PCI bus interfaces that corresponds to the newest transaction request causing the address match, if the transaction addresses from two or more of said plurality of PCI bus interfaces are not the same nor are the transaction addresses within M bytes then no address match signal is generated.

8 more elements

providing a central processing unit connected to a host bus;
providing a random access memory connected to a random access memory bus;
providing a core logic chip set connected to the host bus and the random access memory bus;
configuring said core logic chip set as a first interface bridge between the host bus and the random access memory bus;
configuring said core logic chip set as a plurality of second interface bridges between the host bus and a plurality of peripheral component interconnect (PCI) buses, wherein the plurality of PCI buses are physically separate but have the same logical PCI bus number;
configuring said core logic chip set as a plurality of third interface bridges between the random access memory bus and the plurality of PCI buses;
configuring said core logic chip set as a plurality of fourth interface bridges between the plurality of PCI buses
providing a PCI address comparator;
providing a PCI arbiter for receiving request signals from and issuing grant signals to PCI devices connected to said plurality of PCI buses;
and
providing a PCI target flow controller;
said PCI address comparator receiving transaction addresses from said plurality of PCI bus interfaces, wherein the transaction addresses are compared and an address match is found if the transaction addresses from two or more of said plurality of PCI bus interfaces are the same or are within M bytes of each other, where M=16.times.2.sup.n and n is zero or a positive integer number, then said PCI address comparator sends an address match signal to said PCI target flow controller which causes a retry signal to be issued from the one of said plurality of PCI bus interfaces that corresponds to the newest transaction request causing the address match, if the transaction addresses from two or more of said plurality of PCI bus interfaces are not the same nor are the transaction addresses within M bytes then no address match signal is generated.

9 more elements

A core logic chip set capable of bridging between a processor host bus, memory bus and a plurality of peripheral component interconnect (PCI) buses wherein the plurality of PCI buses each have the same logical PCI bus number, comprising:

a plurality of PCI bus read/write queues;
a plurality of PCI bus interfaces adapted for connection to a plurality of PCI buses;
said plurality of PCI bus read/write queues connected to said plurality of PCI bus interfaces, wherein read and write transactions through said plurality of PCI bus interfaces are stored in said plurality of PCI bus read/write queues;
processor read/write queues;
a processor interface connected to said processor read/write queues, said processor interface adapted for connection to a processor host bus;
random access memory read/write queues;
a random access memory interface connected to said random access memory read/write queues, said random access memory interface adapted for connection to a random access memory bus;
said random access memory queues connected to said processor read/write queues;
said plurality of PCI bus read/write queues connected to said random access memory queues;
said plurality of PCI bus read/write queues connected to said processor read/write queues;
a PCI address comparator;
a PCI arbiter adapted for receiving request signals from and issuing grant signals to PCI devices connected to said plurality of PCI buses;
and
a PCI target flow controller;
said PCI address comparator adapted to receive transaction addresses from said plurality of PCI bus interfaces, wherein the transaction addresses are compared and an address match is found if the transaction addresses from two or more of said plurality of PCI bus interfaces are the same or are within M bytes of each other, where M=16.times.2.sup.n and n is zero or a positive integer number, then said PCI address comparator sends an address match signal to said PCI target flow controller which causes a retry signal to be issued from the one of said plurality of PCI bus interfaces that corresponds to the newest transaction request causing the address match, if the transaction addresses from two or more of said plurality of PCI bus interfaces are not the same nor are the transaction addresses within M bytes then no address match signal is generated.

12 more elements

Dependencies are inferred from the claim text.