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AssigneeHitachi, Ltd.
InventorsKenichi Hase, Ryutaro Horita, Kunio Watanabe, Yoshiteru Ishida, Takashi Nara, Hiroshi Kimura
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A signal processing delay circuit is fabricated as a semiconductor integration circuit to cope with increase in the data transfer speed and data recording and reproducing density on a recording medium. In the delay circuit, the amount of delay of a reference delay circuit of a delay PLL is controlled to take a fixed value independent of deviation in quality of the semiconductor circuit, change in power, and alteration in temperature. A control signal supervising the delay amount of the reference delay circuit is employed to control amounts of delay of input signals supplied to a window adjustment delay circuit of a window adjustment circuit and a T/2 generation delay circuit generating a synchronizing signal. Each of these delay circuits includes an analog variable delay circuit having the same configuration. The window adjustment delay circuit is supervised by a signal obtained by weighting the control signal by a D/A converter. A data acquisition circuit and a data write circuit each include an analog variable delay circuit.
A data acquisition circuit for acquiring sampled data in response to a sampling clock signal synchronized with input data thereto, comprising a phase adjustment circuit for achieving a phase adjustment of the sampled data, wherein the phase adjustment circuit includes a signal processing delay circuit including first delay means including first analog variable delay circuit of which an amount of delay is controlled according to an external reference signal, the first delay means generating a delay amount control signal and second delay means including second analog variable delay circuit in which an amount of delay of an input signal thereto is controlled according to the delay amount control signal generated by the first delay means.
A signal recording and reproducing system, comprising:
Dependencies are inferred from the claim text.