Insertable/removable digital memory apparatus and methods of operation thereof

A storage apparatus comprising:

• a generally rectangular elongated body having first and second substantially planar opposing major surfaces and first and second ends and comprising a main portion and a substrate portion;
• an array of electrical contact pads integral with the body and disposed generally in the plane of the first major surface and extending substantially across a portion of the first major surface proximate the first end, the electrical contact pad array including a data pad, a power pad, a ground pad, and a clock pad, the electrical contact pad array further being disposed on a second side of the substrate portion opposing the first side and substantially coplanar with the first major surface;
• a serial data line integral with the body and coupled to the data pad;
• a power line integral with the body and coupled to the power pad;
• a ground line integral with the body and coupled to the ground pad;
• a clock line integral with the body and coupled to the clock pad;
• a high density memory integrated circuit integral with the body, the memory integrated circuit having a serial data port coupled to the serial line, a power node coupled to the power line, a ground node coupled to the ground line, and a clock node coupled to the clock line, and the memory integrated circuit being disposed on a first side of the substrate portion and in a cavity of the main body portion;
• and
• an additional memory integrated circuit disposed on the first side of the substrate portion and in the cavity of the main body portion, the additional memory integrated circuit having a serial data port coupled to the serial line, a power node coupled to the power line, a ground node coupled to the ground line, and a clock node coupled to the clock line.

A storage apparatus comprising:

• a generally rectangular elongated body having first and second substantially planar opposing major surfaces and first and second ends;
• an array of electrical contact pads integral with the body and disposed generally in the plane of the first major surface and extending substantially across a portion of the first major surface proximate the first end, the electrical contact pad array including a data pad, a power pad, a ground pad, and a clock pad;
• a serial data line integral with the body and coupled to the data pad;
• a power line integral with the body and coupled to the power pad;
• a ground line integral with the body and coupled to the ground pad;
• a clock line integral with the body and coupled to the clock pad;
• a high density memory integrated circuit integral with the body, the memory integrated circuit having a serial data port coupled to the serial line, a power node coupled to the power line, a ground node coupled to the ground line, and a clock node coupled to the clock line, and the memory integrated circuit being disposed on the first major surface;
• and
• an additional memory integrated circuit disposed on the second major surface, the additional memory integrated circuit having a serial data port coupled to the serial line, a power node coupled to the power line, a ground node coupled to the ground line, and a clock node coupled to the clock line.

A storage apparatus comprising:

• a generally rectangular elongated body having first and second substantially planar opposing major surfaces and first and second ends, the body being about 15 mm wide, from about 54 to 25 MM long, and about 0.8 mm thick;
• an array of electrical contact pads integral with the body and disposed generally in the plane of the first major surface and extending substantially across a portion of the first major surface proximate the first end, the electrical contact pad array including a data pad, a power pad, a ground pad, and a clock pad;
• a serial data line integral with the body and coupled to the data pad;
• a power line integral with the body and coupled to the power pad;
• a ground line integral with the body and coupled to the ground pad;
• a clock line integral with the body and coupled to the clock pad;
• and
• a high density memory integrated circuit integral with the body, the memory integrated circuit having a serial data port coupled to the serial line, a power node coupled to the power line, a ground node coupled to the ground line, and a clock node coupled to the clock line.

A method for detecting endwise insertion of a card into a socket, comprising:

• arrange a ground pad and a card detect pad on the card generally in the direction of insertion of the card into the socket;
• activate a detect control signal coupled to the card detect pad through a resistive element;
• monitor the card detect pad to determine whether the active detect control signal is asserted on the card detect pad and attempt to perform a card read operation, wherein:
• if the active detect control signal is present on the card detect pad and the read operation is successful, the card is properly inserted and is not write protected;
• if the active detect control signal is present on the card detect pad and the read operation is not successful, the card is not inserted;
• if the active detect control signal is not present on the card detect pad and the read operation is successful, the card is properly inserted and is write protected;
• and
• if the active detect control signal is not present on the card detect pad and the read operation is not successful, the card is not properly inserted.

A method for protecting electronic circuits during edgewise removal of a card from a socket, comprising:

• arrange a ground pad and a card detect pad on the card generally in the direction of insertion of the card into the socket;
• activate a detect control signal coupled to the card detect pad through a resistive element;
• monitor the card detect pad to determine whether the active detect control signal is asserted, wherein a substantial period of active detect control signal on the card detect pad followed by a substantial period of inactive detect control signal on the card detect pad is indicative of card removal;
• and
• power down circuits coupled to the card when card removal is indicated.