Correlated double sampling with up/down counter
AssigneeInternational Business Machines Corporation
InventorsSudhir Muniswamy Gowda, Hyun Jong Shin, Hon-Sum Philip Wong, Peter Hong Xiao, Jungwook Yang
Life of this patent
Estimating the term…
Loading patent…
AssigneeInternational Business Machines Corporation
InventorsSudhir Muniswamy Gowda, Hyun Jong Shin, Hon-Sum Philip Wong, Peter Hong Xiao, Jungwook Yang
Estimating the term…
Disclosed is a circuit for performing correlated double sampling entirely in the digital domain. In an exemplary embodiment, the circuit includes a plurality of comparators, each having a first input coupled to an associated data line for receiving first and second signals in first and second sampling intervals, respectively. A time varying reference signal is applied to the second input of each comparator. A plurality of up/down counters are coupled to respective ones of the comparators, and each is operable to count in a first direction during the first sampling interval and in an opposite direction during the second sampling interval. Each up/down counter is caused to stop counting when the amplitude of the variable reference signal substantially equals the amplitude of the respective first or second signal. As a result, each up/down counter provides an output representing a subtraction of one of said first or second signals from the other. The invention has particular utility when used in conjunction with a CMOS image sensor.
A circuit for performing correlated double sampling, comprising:
An image sensing device having correlated double sampling circuitry, said image device comprising:
A method for performing correlated double sampling, comprising the steps of:
Dependencies are inferred from the claim text.