Method for forming advanced transistor structures with optimum short channel controls for high density/high performance integrated circuits
AssigneeAdvanced Micro Devices, Inc.
InventorsYowjuang W. Liu, Kuang-Yeh Chang
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Abstract
A novel MOS transistor structure for improving device scaling by improving short channel control includes a buried back gate beneath a channel region of the MOS transistor. A separate contact to a well that is electrically communicated to the buried back gate improves short channel controls without performance degradations. In a preferred embodiment, the back gate is grounded when turning the n-channel MOS transistor off. In alternate embodiments, the buried layer produces retrograde p wells. In some applications, multiple buried layers may be used, with one or more being planar. CMOS devices may have independent, multiple buried back gates.
Claims13
A method for forming a semiconductor device, comprising the steps of:
- forming, coupled to a substrate having a first conductivity-type, a first active region and a second active region separated from each other by a channel region wherein a gate overlies said channel region, said active regions being a second conductivity-type;
- forming, in said substrate, a well region of said second conductivity isolated from said active regions by an isolation region;
- thereafter
- implanting dopants of said second conductivity-type into said substrate through said active regions, said gate, said isolation region and said well region to form a first deep implant region that underlies said channel region and is electrically communicated to said well region;
- implanting dopants of said second conductivity-type into said active regions and said well region;
- and thereafter
- annealing said substrate to produce a buried structure from said first implant region.
A method for forming a semiconductor device, comprising the steps of:
- forming, coupled to a substrate having a first conductivity-type, a first active region and a second active region separated from each other by a channel region wherein a gate overlies said channel region, said active regions being a second conductivity-type;
- forming, in said substrate, a well region of said second conductivity isolated from said active regions by an isolation region;
- thereafter
- forming an implant mask over said substrate, said implant mask having exposure regions overlying said active regions, said gate, said isolation region and said well region;
- implanting dopants of said second conductivity-type through said exposure regions of said implant mask to produce a first implant region that underlies said channel region and is electrically communicated to said well region
- implanting dopants of said second conductivity-type through said exposure regions of said implant mask into said active regions and said well region;
- and thereafter
- annealing said substrate to produce a buried structure from said first deep implant region.
A method for forming a semiconductor device, comprising the steps of:
- implanting a buried layer implant in a substrate having a first conductivity-type, said buried layer having a second conductivity type;
- thereafter
- forming, coupled to said substrate, a first active region and a second active region overlying said implant separated from each other by a channel region wherein a gate overlies said channel region, said active regions being a second conductivity-type;
- forming, in said substrate, a well region of said second conductivity isolated from said active regions by an isolation region, said well region electrically communicated to said buried layer;
- thereafter
- implanting dopants of said second conductivity-type into said active regions and said well region;
- and thereafter
- annealing said substrate to produce a buried structure from said buried implant.
The method of 12 wherein said buried structure is planar.
Dependencies are inferred from the claim text.