US 5,875,352 A · Method and apparatus for multiple channel direct memory access control

Abstract

An on-chip cache memory is used to provide a high speed access mechanism to frequently used channel state information for operation of a DMA device that supports multiple virtual channels in a high speed network interface. When an access to a particular channel state is performed, e.g., by a host processor or the DMA device, the cache is first accessed and if the state information is not located currently in the cache, external memory is read and the state information is written to the cache. As the cache does not store all the states stored in external memory, replacement algorithms are utilize to determine which channel state information to remove from the cache in order to provide room to store a recently accessed channel. A doubly linked list is used to track the most recently used channel. As cached channel information is accessed, the corresponding entry is moved to the top of the list. The doubly linked list provides a rapid apparatus and method for updating pointers to the cache. Top and bottom pointers are maintained, pointing to the most recently used and least recently used channels. When a channel is used, it moved to the top of the list. When channel data is moved from external memory to the cache, the bottom pointer points to the channel data to be removed from the cache.

Claims20

Dependent claims

A network switch interface comprising:

interface circuitry for coupling data among at least one host computer and at least one of a plurality of channels of a network;
a memory coupled to the interface circuitry for storing a plurality of channel information for the plurality of channels, each channel information utilized to transfer data among the plurality of channels using at least one network switch;
a cache coupled to the interface circuitry comprising cache entries of recently used channel information;
a MRU list of the cache comprising a plurality of list entries, each list entry corresponding to a cache entry in the MRU cache;
a direct memory access (DMA) controller coupled to the interface circuitry for transferring the received data among the plurality of channels in accordance with corresponding channel information, said DMA controller accessing the cache to retrieve the corresponding channel information for the corresponding channel, if the corresponding channel information is not stored in the cache, said DMA controller accessing external memory to retrieve the corresponding channel information and store the corresponding channel information in the cache, said DMA controller further updating the MRU list to identify a current cache entry containing the corresponding channel information as most recently used.

2 more elements

A method for multiple channel direct memory access (DMA) control of a network switch interface, the method comprising the steps of:

receiving data from at least one of a plurality of channels of a network;
storing a plurality of channel information for the plurality of channels,
wherein the channel information is used to transfer data among the plurality of channels of at least one network switch;
transferring the received data among the plurality of channels in accordance with corresponding channel information using a DMA controller, said DMA controller accessing a cache to retrieve the corresponding channel information for the corresponding channel, if the corresponding channel information is not stored in the cache, said DMA controller accessing an external memory to retrieve the corresponding channel information and store the corresponding channel information in the cache, said DMA controller further updating an MRU list to identify a current cache entry containing the corresponding channel information as most recently used.

1 more element

Dependencies are inferred from the claim text.

Method and apparatus for multiple channel direct memory access control

Life of this patent

Method and apparatus for multiple channel direct memory access control

Life of this patent

Abstract

Claims20