US 5,875,293 A · System level functional testing through one or more I/O ports of an assembled computer system

Abstract

A test apparatus and method for fully testing the functional aspects of a computer system at the system level through one or more of its I/O ports. A test system is connected to an externally available I/O port of the computer under test for accessing its system ROM and a jumper is installed on the computer under test to disable its system ROM. The jumper also bypasses the PCMCIA controller, if necessary, to provide the test system direct access to the I/O port and thus the system ROM. The computer under test is booted from diagnostic test code stored in memory of the test system, where the diagnostic test code has complete control and performs a series of tests on the computer under test. Other I/O ports of the computer under test, including its serial ports, parallel port, keyboard and mouse ports, video port and a docking port may also be connected to the test system, if desired. Certain portions of the diagnostic test code may be downloaded into video RAM of the computer under test and executed sequentially. Also, a communication protocol may be established between the host computer and the computer under test so that the host computer can control initiation and monitor status of each test routine.

Claims36

Dependent claims

A test apparatus for testing operations of a computer system, comprising:

a test circuit, comprising:
memory for storing diagnostic code;
and
an I/O port coupled to said memory;
and
a computer system under test, comprising:
an I/O bus;
a PCMCIA port including a PCMCIA controller coupled to said I/O bus and an external PCMCIA connector coupled to said PCMCIA controller and for coupling to said I/O port of said test circuit;
an external disable mechanism that provides a disable signal;
a bypass circuit that receives said disable signal and correspondingly bypasses said PCMCIA controller to couple signal lines of said I/O bus to said PCMCIA connector;
and
a processor coupled to said I/O bus, wherein said processor boots from said test circuit memory through said PCMCIA port and said test circuit I/O port upon power up and executes said diagnostic code.

9 more elements

Dependencies are inferred from the claim text.

System level functional testing through one or more I/O ports of an assembled computer system

Life of this patent

System level functional testing through one or more I/O ports of an assembled computer system

Life of this patent

Abstract

Claims36