Method and apparatus for error injection techniques

An information processing system comprising:

• a processor device;
• a memory device;
• a memory controller connected between said processor and said memory device;
• a data path controller connected between said processor and said memory device;
• and
• a masking device connected to said memory device, said masking device being selectively responsive to masking signals applied thereto for masking selected data paths between said data path controller and said memory device.

A storage medium including machine readable indicia, said storage medium being selectively coupled to a reading device, said reading device being coupled to processing circuitry, said reading device being selectively operable to read said machine readable indicia and provide program signals representative thereof, said program signals being effective to cause said processing circuitry to test a memory by performing the steps of:

• clearing said memory;
• writing a first test pattern of test signals to said memory;
• blocking predetermined data paths to said memory;
• writing a second test pattern of test signals to said memory;
• unblocking the data paths to said memory;
• and
• reading predetermined memory locations in said memory to provide an readout pattern.