High reliability I/O stacked fets

A complementary metal oxide semiconductor (CMOS) mixed voltage input/output (I/O) driver circuit comprising:

• a stack of at least first and second serially connected CMOS devices of the same type, said first CMOS device being connected to an I/O pad and said second CMOS device being connected to a voltage source;
• voltage control means for preventing a node between the serially connected first and second devices from charging to a voltage greater than a predetermined voltage;
• said stack further including at least third and fourth serially connected CMOS devices of a type opposite the type of said first and second CMOS devices, said third CMOS device being connected to said I/O pad and said fourth CMOS device being connected to a second voltage source opposite to said first mentioned voltage source, further comprising second voltage control means for preventing a second node between the third and fourth serially connected devices from charging to a voltage greater than a second predetermined voltage;
• and
• wherein said first mentioned voltage control means comprises a first clamping diode connected between said first mentioned node between the serially connected first and second CMOS devices and a gate of said first CMOS device, thereby clamping said first mentioned node to a voltage at the gate of said first CMOS device, and wherein said second voltage control means comprises a second clamping diode connected between said second node between the serially connected third and fourth CMOS devices and a gate of said third CMOS device, thereby clamping said second node to a voltage at the gate of said third CMOS device.

High reliability input/output (I/O) stacked field effect transistors (FETs) wherein the effects of across chip length variation (ACLV), gate ion channeling and dislocation are reduced or eliminated, comprising:

• first and second stacked PFETs;
• first and second stacked NFETs;
• and
• an I/O pad, said first PFET and said first NFET being connected to the I/O pad, said first PFET and said first NFET being designed with a channel length greater than the second PFET and the second NFET, respectively, thereby making the first PFET and the first NFET insensitive to leakage-induced effects.

High reliability input/output (I/O) stacked field effect transtors (FETs) wherein the effects of across chip length variation (ACLV), gate ion channeling and dislocation are reduced or eliminated, comprising:

• first and second stacked PFETs;
• first and second stacked NFETs;
• an I/O pad, said first PFET and said first NFET being connected to the I/O pad;
• and
• first and second diodes, said first diode connected between a node between said first and second PFETs and a gate of the first PFET, and said second diode connected between a node between said first and second NFETs and a gate of the first NFET, said first and second diodes acting to clamp the nodes between the first and second PFETs and the first and second NFETs near the respective gate voltages of the first PFET and of the first NFET, thereby making the first PFET and the first NFET insensitive to leakage-induced effects.

High reliability input/output (I/O) stacked field effect transistors (FETs) wherein the effects of across chip length variation (ACLV), gate ion channeling and dislocation are reduced or eliminated, comprising:

• first and second stacked PFETs;
• first and second stacked NFETs;
• an I/O pad, said first PFET and said first NFET being connected to the I/O pad;
• and
• a third NFET connected between a node between said first and second PFETs and a gate of the first PFET, a gate of the third NFET being connected to a gate of the second PFET;
• and
• a third PFET connected between a node between said first and second NFETs and a gate of the first PFET, a gate of the third PFET being connected to a gate of the second NFET, said third NFET and said third PFET acting to clamp the nodes between the first and second PFETs and the first and second NFETs near the respective gate voltages of the first PFET and of the first NFET, thereby making the first PFET and the first NFET insensitive to leakage-induced effects.