Apparatus for generating timing signals for a digital television signal receiver

Apparatus for generating timing signals from digital television signals, comprising:

• a filter/complement for filtering said digital television signals having a first output terminal producing a low-pass filtered signal, and a second output terminal producing a high-pass filtered signal complementary to the low-pass filtered signal;
• and
• a sample clock generating circuit, coupled to the second output terminal of the filter/complement, for producing a sample clock signal responsive to the high-pass filtered signal said sample clock generating circuit comprising a band edge timing recovery circuit;
• wherein the high-pass filtered signal is a simple real signal which contains a positive frequency component and a negative frequency component, and the sample clock generating circuit comprises:
• a first band edge filter, coupled to the filter/complement, for extracting one of the positive and negative frequency components from the high-pass filtered signal;
• a complex conjugating circuit, coupled to the filter/complement;
• a second band edge filter, coupled to the complex conjugating circuit, for extracting the other one of the positive and negative frequency components from the high-pass filtered signal;
• a first phase detector, coupled to the first band edge filter;
• a second phase detector, coupled to the second band edge filter;
• a subtractor, having a minuend input terminal coupled to the first phase detector, and a subtrahend input terminal coupled to the second phase detector;
• and
• a series connection of a loop filter and a voltage controlled oscillator coupled to a signal combiner and producing the sample clock signal.

Apparatus for generating timing signals from digital television signals, comprising:

• a filter/complement for filtering said digital television signals having a first output terminal producing a low-pass filtered signal, and a second output terminal producing a high-pass filtered signal complementary to the low-pass filtered signal;
• and
• a sample clock generating circuit, coupled to the second output terminal of the filter/complement, for producing a sample clock signal responsive to the high-pass filtered signal, said sample clock generating circuit comprising a band edge timing recovery circuit;
• wherein:
• the second output terminal of the filter/complement comprises a real component signal output terminal and an imaginary component signal output terminal, and the high-pass filtered signal contains a positive frequency component and a negative frequency component;
• and
• the sample clock generating circuit comprises:
• a first band edge filter, having a real signal input terminal coupled to the real signal output terminal of the filter/complement, and an imaginary signal input terminal, for extracting one of the positive and negative frequency components from the high-pass filtered signal;
• a first multiplexer, having a first data input terminal coupled to the imaginary component signal output terminal of the filter/complement, a second data input terminal coupled to a source of a zero-valued signal, an output terminal coupled to the imaginary signal input terminal of the first band edge filter, and a control input terminal;
• a controllable I/Q swapper circuit, having respective real and imaginary signal input terminals coupled to corresponding output terminals of the filter/complement, respective real and imaginary signal output terminals, and a control input terminal;
• a second band edge filter, having a real signal input terminal coupled to the real signal output terminal of the controllable I/Q swapper circuit, and an imaginary signal input terminal, for extracting the other one of the positive and negative frequency components from the high-pass filtered signal;
• a second multiplexer, having a first data input terminal coupled to the imaginary signal output terminal of the controllable I/Q swapper circuit, a second data input terminal coupled to the source of a zero-valued signal, an output terminal coupled to the imaginary signal input terminal of the second band edge filter, and a control input terminal;
• a complex conjugating circuit, coupled to the second band edge filter;
• a complex multiplier, having a first input terminal coupled to the first band edge filter, and a second input terminal coupled to the complex conjugating circuit;
• a complex multiplexer, having a first input terminal coupled to the first band edge filter, a second input terminal coupled to the complex multiplier, and a control input terminal;
• a first phase detector, coupled to the complex multiplexer;
• a second phase detector, coupled to the second band edge filter;
• a third multiplexer, having a first data input terminal coupled to the second phase detector, a second data input terminal coupled to the source of a zero-valued signal, and a control input terminal;
• a subtractor, having a minuend input terminal coupled to the first phase detector, and a subtrahend input terminal coupled to the third multiplexer;
• a series connection of a loop filter and a voltage controlled oscillator coupled to a signal combiner and producing the sample clock signal;
• and
• a source of control signal having one of a first and second state, coupled to respective control input terminals of the controllable I/Q swapper circuit, the first, second and third multiplexers, and the complex multiplexer;
• wherein:
• when the control signal is in the first state:
• the first multiplexer is conditioned to couple the signal from the filter/complement to the first band edge filter;
• the controllable I/Q swapper circuit is conditioned to pass the signal from the filter/complement to its respective output terminals unchanged;
• the second multiplexer is conditioned to couple the signal from the controllable I/Q swapper circuit to the second band edge filter;
• the complex multiplexer is conditioned to couple the signal from the complex multiplier to the first phase detector;
• and
• the third multiplexer is conditioned to couple the signal from the zero-valued signal source to the subtractor;
• and
• when the control signal is in the second state:
• the first multiplexer is conditioned to couple the signal from the zero-valued signal source to the first band edge filter;
• the controllable I/Q swapper circuit is conditioned to pass swapped I/Q data signals from the filter/complement to its respective output terminals;
• the second multiplexer is conditioned to couple the signal from the zero-valued signal source to the second band edge filter;
• the complex multiplexer is conditioned to couple the signal from the first band edge filter to the first phase detector;
• and
• the third multiplexer is conditioned to couple the signal from the second phase detector to the subtractor.

In a receiver for television signals, apparatus for sampling said television signals comprising:

• an analog-to-digital (A/D) converter for periodically sampling said television signals in response to a timing signal to produce sampled television signals;
• a quadrature demodulator, coupled to said A/D converter, for demodulating said sampled television signals into an in-phase component and a quadrature component;
• a first matched filter/complement, coupled to said quadrature demodulator, for filtering said in-phase component having a first output terminal producing an in-phase low pass filtered signal, and a second output terminal having an in-phase high pass filtered signal complementary to the in-phase low pass filtered signal;
• a second matched filter/complement, coupled to said quadrature demodulator, for filtering said quadrature component having a first output terminal producing a quadrature low pass filtered signal, and a second output terminal having a quadrature high pass filtered signal complementary to the quadrature low pass filtered signal;
• and
• a timing signal generating circuit, coupled to the second output terminals of the first and second filter/complements, for producing the timing signal for said A/D converter.