Back to results
US 5,872,446 AGranted
Low voltage CMOS analog multiplier with extended input dynamic range
AssigneeInternational Business Machines Corporation
InventorsHayden Clavie Cranford, Jr., Ronald Steven Gyurcsik, James Francis McElwee, Jr.
Life of this patent
Estimating the term…
Abstract
A low voltage CMOS multiplier uses a transconductance stage to generate a dynamic bias current which is used to compensate for non-linear terms in a Gilbert Cell multiplier circuit. Common mode dependence is minimized by using balanced differential input stages for both the transconductance and multiplier stages.
Claims5
A circuit for multiplying two signals represented by two analog voltages V.sub.x and V.sub.y comprising:
- a transconductance circuit responsive to V.sub.x for converting V.sub.x to a related first current (I.sub.tran);
- and,
- a Gilbert Cell core multiplier having two n-channel cross coupled differential transistor pairs responsive to said voltage V.sub.x and providing a second current (I.sub.x, I.sub.y) related to the value of V.sub.x, a folded p-channel transistor pair responsive to the voltage V.sub.y and providing a third current (I.sub.y1, I.sub.y2) related to the voltage V.sub.y, and a current source (M14,M15) under control of said first current for combining said second and third currents whereby the voltage output (V.sub.out) of the said Gibert Cell core is a linear representation of the product of V.sub.x and V.sub.y.
Dependencies are inferred from the claim text.