Multi-bank memory input/output line selection
AssigneeMicron Technology, Inc.
InventorsBrent Keeth, Troy A. Manning
Life of this patent
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AssigneeMicron Technology, Inc.
InventorsBrent Keeth, Troy A. Manning
Estimating the term…
A multi-bank memory includes memory cells arranged in individually selectable banks that share column select signals. The memory cells are addressed by a row decoder that activates word lines to couple data onto digit lines. The digit lines are coupled to input/output lines through first and second series-connected switches. The first switches are input/output switches that are controlled by column select signals that are shared between multiple banks. The second switches are bank select switches that are controlled by a bank decoder, for coupling only one of the banks to input/output lines and isolating the other banks from input/output lines. The invention reduces timing requirements between operations in different banks, and allows concurrent operations in different banks, thereby increasing the speed at which the memory operates.
A memory comprising:
A memory comprising a column of memory cells arranged in separately addressable banks, the memory cells being selectively coupled to an input/output line through first and second series-coupled switches, wherein the first switch is an input/output switch that is controlled by a column select signal, and the second switch is a bank switch that is controlled by a bank select signal.
A memory comprising:
A method of using a memory cell array including memory cells arranged in separately addressable banks that share column select signals for addressing the memory cells, the method comprising the steps of:
A method of coupling memory cells in a multi-bank memory to input/output lines, the method comprising the steps of:
A method of coupling a column of memory cells to an input/output line, the method comprising the steps of:
An electronic system, comprising:
Dependencies are inferred from the claim text.