Advanced massively parallel computer with a secondary storage device coupled through a secondary storage interface
AssigneeSarnoff Corporation
InventorsDanny Chin, Joseph Edward Peters, Jr., Herbert Hudson Taylor, Jr.
Life of this patent
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Abstract
An advanced massively parallel computer having a plurality of processor subsystems, where each processor subsystem is coupled to a secondary storage device (e.g., disk drive) through a secondary storage interface. The computer contains an input data bus for supplying data to the processor subsystem, an interprocessor communications bus for communicating data and instructions between processor subsystems, and an instruction bus for supplying instructions to the processor subsystems to facilitate data manipulation by each of the processor subsystems.
Claims11
A parallel processing computer system comprising:
- a plurality of identical processor subsystems for performing data manipulation, including arithmetic and logical computations;
- an input data bus, coupled to each of the processor subsystems, for supplying data to the plurality of processor subsystems;
- an instruction bus, coupled to each of the processor subsystems, for supplying instructions to the plurality of processor subsystems to control said data manipulation;
- and
- an interprocessor communications (IPC) means, coupled to each of the processor subsystems, for communicating data and instructions between processor subsystems within said plurality of processor subsystems;
- where each identical processor subsystem comprises:
- a source of clock signal having a predetermined frequency;
- a processor for performing said data manipulations;
- memory, coupled to said processor, for storing a plurality of data values;
- a secondary storage device;
- and
- a secondary storage interface, coupled to the secondary storage device and the processor, responsive to commands from the processor, for writing data to the secondary storage device and reading data from the secondary storage device;
- where each processor performs said data manipulation using data stored in said memory, data stored in said secondary storage device or data provided by said input data bus;
- and
- where the IPC means comprises:
- a bus, coupled to each of the processor subsystems, including means for conveying a data clock signal which causes the IPC means to transfer one of said data values on the bus for each pulse of the data clock signal;
- and
- means, responsive to control information conveyed via the instruction bus, for providing the data clock signal at a first frequency substantially equal to the predetermined frequency and for providing the data clock signal at a second frequency approximately equal to N-times the predetermined frequency, where N is an integer greater than 1.
Dependencies are inferred from the claim text.