High density interconnected circuit module with a compliant layer as part of a stress-reducing molded substrate

An integrated circuit module, comprising:

• a plurality of chips formed of a material having a first coefficient-of-temperature-expansion (CTE), each of said chips having contact pads located on a face thereof and all of said chips pads being substantially in a common plane;
• at least one layer of a substantially-solid, compliant material having a second CTE different from said first CTE, and disposed around and between said chips and extending from said common face plane of said chips at least a substantial portion of the distance to the backsides of said chips;
• hardened substrate molding material, having a third CTE different from the CTE of said compliant material, and surrounding said compliant material below said common face plane;
• a dielectric layer situated on at least portions of said compliant material, the faces of said chips and said hardened substrate molding material, said dielectric layer including a plurality of vias therein, at least some of said plurality of vias being aligned with predetermined ones of said contact pads, respectively;
• and
• a pattern of electrical conductors extending through selected ones of said plurality of vias in said dielectric layer.