Differential amplifier circuit with enlarged range for source voltage and semiconductor device using same

A differential amplifier circuit comprising:

• a differential amplifier having an inversion input terminal and a non-inversion input terminal;
• and
• input amplifiers including one input amplifier which is connected to said inversion terminal and another input amplifier which is connected to said non-inversion terminal of said differential amplifier, each of said input amplifiers functioning so as to supply to said differential amplifier an output voltage corresponding to any input voltage within a first range received thereby, said output voltage changing with respect to said input voltage within a second range which is smaller than said first range, each of said input amplifiers comprising:
• a CMOS buffer circuit having an output line connected to said differential amplifier;
• and
• impedance elements including one impedance element connected between said output line and a reference voltage V.sub.ref and another impedance element connected between said output line and a source voltage V.sub.DD ;
• said differential amplifier comprising n-type and p-type MOS transistors with threshold voltages given respectively by V.sub.thn and V.sub.thp, and being connected to said source voltage V.sub.DD and said reference voltage V.sub.ref, said first range being between V.sub.ref and V.sub.DD, said second range being between V.sub.DD -1.5V.sub.thp and V.sub.ref +1.5V.sub.thn.

A semiconductor circuit comprising:

• a differential amplifier having an inversion input terminal and a non-inversion input terminal;
• input amplifiers including one input amplifier which is connected to said inversion terminal and another input amplifier which is connected to said non-inversion terminal of said differential amplifier, each of said input amplifiers functioning so as to supply to said differential amplifier an output voltage corresponding to any input voltage within a first range received thereby, said output voltage changing with respect to said input voltage within a second range which is smaller than said first range;
• and
• a bias circuit connected to said differential amplifier and adapted to supply a bias voltage to said differential amplifier, each of said input amplifiers comprising:
• a CMOS buffer circuit having an output line connected to said differential amplifier;
• and
• impedance elements including one impedance element connected between said output line and a reference voltage V.sub.ref and another impedance element connected between said output line and a source voltage V.sub.DD ;
• said differential amplifier comprising n-type and p-type MOS transistors with threshold voltages given respectively by V.sub.thn and V.sub.thp, and being connected to said source voltage V.sub.DD and said reference voltage V.sub.ref, said first range being between V.sub.ref and V.sub.DD, said second range being between V.sub.DD -1.5V.sub.thp and V.sub.ref +1.5V.sub.thn.