US 5,862,502 AGranted

Circuit arrangement for safety-critical control systems

AssigneeITT Automotive Europe GmbH

InventorBernhard Giers

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Abstract

A circuit arrangement for safety-critical control systems, for example, for the control of anti-lock brake systems, is based on an at least partly redundant processing of input data which are taken into account for generating control signals. The control system is disconnected upon non-correlation of the signals. A microprocessor system is provided for data processing and includes two or more central processor units permitting parallel processing of the input data. The output data of the CPUs are checked for correlation. Each write/read memory of the microprocessor system has a generator to generate a test information. The write/read memories and the read-only memories are extended by memory spaces for the test information. In every writing or reading access to the memories, the contents of the memory space is tested with the associated test information for correlation, and an error identification signal is generated in the absence of correlation or plausibility.

Claims20

Dependent claims

A circuit arrangement for use in safety-critical control systems, comprising:

(a) input means for receiving an input signal;
(b) a microprocessor system including:
(i) at least two central processor units for processing the input signal in parallel and each generating a respective output signal,
(ii) a comparator for comparing said respective output signals and generating an error identification signal if the respective output signals do not correlate;
(iii) at least one common memory having a writing access and a reading access;
(iv) a test information generator corresponding to each at least one common memory for generating first test information corresponding to information to be written to said at least one common memory and second test information corresponding to information to be read from said at least one common memory;
and
(v) a test information memory corresponding to each at least one common memory for storing said first test information;
and
(c) means responsive to said writing access of said at least one common memory for causing the corresponding test information generator to generate said first test information and storing said first test information in the corresponding test information memory;
and
(d) means responsive to said reading access of the at least one common memory for causing the corresponding test information generator to generate said second test information, comparing said first test information with said second test information, and generating an error identification signal if said first test information and said second test information do not correlate.

9 more elements

Dependencies are inferred from the claim text.