Memory LSI with arithmetic logic processing capability, main memory system using the same, and method of controlling main memory system

A main memory with arithmetic logic processing capability, comprising:

• a memory bus;
• k first memories (k is an integer equal to or more than 0) connected to said memory bus, for storing data;
• and
• m second memories with arithmetic logic processing capability (m is an integer equal to or more than 1) connected to said memory bus, wherein each of said m second memories comprises:
• a memory section for storing data,
• a storing section for storing at least a macro code, and
• an arithmetic logic processing section for executing said at least a macro code in response to a first instruction inputted via said memory bus to perform a first processing to at least a part of said data stored in said memory section, and for allowing a result of said first processing to be outputted onto said memory bus in response to a second instruction inputted via said memory bus.

A memory device with arithmetic logic processing capability, comprising:

• a memory bus connected to external terminals;
• an internal bus;
• a dynamic random access memory (DRAM) section connected between said memory bus and said internal bus;
• and
• an arithmetic logic processing section connected between said memory bus and said internal bus, for performing a first processing to at least a part of data stored in said DRAM section in response to a first instruction inputted via said memory bus, and for allowing a result of said first processing to be outputted onto said memory bus in response to a second instruction inputted via said memory bus.

A method of controlling a main memory with arithmetic logic processing capability in a processor system including a processor, said main memory comprising at least one memory device with arithmetic logic processing capability, comprising the steps of:

• issuing a first instruction from said processor to said memory device via a memory bus;
• performing a processing to at least a part of data stored in said memory section in said memory device in response to said first instruction;
• storing a processing result in said memory device;
• issuing a second instruction from said processor to said memory device via said memory bus;
• and
• outputting a data designating the processing result to said processor in response to said second instruction inputted via said memory bus.