Method and apparatus for handling bus master and direct memory access (DMA) requests at an I/O controller

Logic circuitry for use in a system controller of a computer system, the computer system including a plurality of agents, the logic circuitry comprising:

• a plurality of inputs coupled to receive resource requests from the plurality of agents via a plurality of request lines, each request line being dedicated to a respective agent;
• decoder circuitry to determine whether each resource request is a DMA request or a bus request;
• routing circuitry to route a resource request to a DMA controller if the resource request is determined by the decoder circuitry to be a DMA request, or to a bus arbiter if the resource request is determined by the decoder circuitry to be a bus request;
• and
• a plurality of outputs to transmit resource grants from the DMA controller and the bus arbiter to the plurality of agents via a plurality of grant lines, each grant line being dedicated to a respective agent.

A method of allocating resources in a computer system including a plurality of agents, a Direct Memory Access (DMA) controller and a bus arbiter, the method comprising the steps of:

• receiving a resource request from an agent at a logic unit via a request line dedicated to the agent;
• determining whether the resource request is a DMA request or a bus request;
• if the resource request is a bus request, then routing the resource request from the logic unit to the bus arbiter and routing a resource grant, responsive to the resource request, from the bus arbiter to the logic unit;
• if the resource request is a DMA request, then routing the resource request from the logic unit to the DMA controller and routing the resource grant, responsive to the resource request, from the DMA controller to the logic unit;
• and
• transmitting the resource grant from the logic unit to the agent via a grant line dedicated to the agent.