Pad cells for a 2/N mode clocking scheme
AssigneeIntel Corporation
InventorsChakrapani Pathikonda, Jeff Wight
Life of this patent
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Abstract
A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.
Claims23
An integrated circuit for use in a computer system having a bus transferring information using a bus clock signal having a frequency, said integrated circuit comprising:
- a plurality of pins;
- a core operable in response to a core clock signal that is a N/2 times the frequency of the bus clock signal, wherein every other phase of the bus clock signal is out of phase with the core clock signal;
- a plurality of pad cells coupling the plurality of pins to the core, wherein each pad cell comprises an input path having first and second latches coupled in series from a pin to the core and an output path having third and fourth latches coupled in series from the pin to the core, wherein the third latch is clocked by the bus clock signal and the second and fourth latches are clocked by first and second core clock signals respectively.
An integrated circuit for use in a computer system having a bus transferring information using a bus clock signal having a frequency, said integrated circuit comprising:
- a plurality of pins;
- a core operable in response to a core clock signal that is a N/2 times the frequency of the bus clock signal, wherein every other phase of the bus clock signal is out of phase with the core clock signal when N is an odd integer greater than two;
- a plurality of pad cells means coupling the plurality of pins to the core, wherein each pad cell comprises an input path means having first and second latching means for transferring information from one of the plurality of pins to the core and an output path means having third and fourth latching means for transferring information from the core to said one of the plurality of pins, wherein the third latching means is clocked by the bus clock signal and the second latching means and the fourth latching means are clocked by first and second core clock signals.
Dependencies are inferred from the claim text.