Method and apparatus for state machine optimization using device delay characteristics

A digital electronic device which operates according to a state machine, said device capable of encoding delay characteristics associated with said device to increase performance of said state machine operations relative to a clocking signal having first and second edges, said device comprising:

• a delay encoder coupled to said state machine for monitoring said delay characteristics associated with said device and for encoding said delay characteristics associated with said device as delay information;
• circuitry which operates according to the state machine, wherein said circuitry includes a present state of said state machine and a next state of said state machine, wherein said circuitry includes an input coupled to said delay encoder which receives said delay information which is a one bit value indicating a fast or slow device;
• wherein said circuitry determines its next state depending on its present state, and on the content of said delay information, wherein said circuitry advances from said present state of said state machine to said next state of said state machine with reference to a first edge of said clocking signal at a first time if said delay information indicates a fast device and said circuitry advances from said present state of said state machine to said next state of said state machine with reference to a second edge of said clocking signal at a second time later than said first time if said delay information indicates a slow device.

A method for increasing operation performance of a device, the device being clocked by a clocking signal having first and second edges, the second edge occurring after the first edge, the device including circuitry for sampling a first signal propagating in a functional path of the device and a device delay encoder, the device delay encoder including a plurality of logic elements coupled within a delay signal path of the device and a plurality of outputs, the plurality of outputs being coupled to at least some of the logic elements, the method comprising:

• propagating a second signal through the delay signal path:
• sampling the plurality of outputs to provide a plurality of delay sample signals;
• encoding the delay sample signals into a delay information bit, the delay information bit indicating a fast or slow device;
• operating the device to sample the first signal propagating in the functional path of the device on the first edge of the clocking signal if the delay information bit indicates a fast device;
• and
• operating the device to sample the first signal propagating in the functional path of the device on the second edge of the clocking signal if the delay information bit indicates a slow device;
• wherein
• the device includes a cache system;
• the first signal propagating in the device includes information from a memory provided to the cache system;
• the cache system includes a cache controller;
• and
• the method further includes
• asserting by the cache controller a bus ready signal on the first edge of the clocking signal if the delay information bit indicates a fast device;
• and
• asserting by the cache controller a bus ready signal on the second edge of the clocking signal if the delay information bit indicates a slow device.