System and method for simulating a multiprocessor environment for testing a multiprocessing interrupt controller
AssigneeAdvanced Micro Devices, Inc.
InventorsRodney Schmidt, Steve Ennis, Michael T. Wisor
Life of this patent
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Abstract
A multiprocessing system comprising a plurality of processors and a plurality of I/O devices. A central interrupt control unit functionally intercouples the plurality of processors and I/O devices. The central interrupt control unit is configured to receive interrupt signals from the I/O devices and is configured to distribute interrupt signals to the processors. One of the processors is configured as a master test processor to control a test mode for testing the central interrupt control unit. The master test processor is further configured to release the other processors and emulate a multiprocessing environment.
Claims22
A multiprocessing system comprising:
- a plurality of processors which includes a test processor and a destination processor other than said test processor;
- a plurality of I/O devices;
- and
- a central interrupt control unit functionally intercoupling said plurality of processors and said plurality of I/O devices, wherein said central interrupt control unit is configured to receive interrupt signals from said plurality of I/O devices and is configured to distribute said interrupt signals to said plurality of processors;
- and
- wherein the test processor is configured to operate in a test mode, wherein in said test mode said test processor intercepts interrupt signals targeted to the destination processor and responds to said interrupt signals with corresponding interrupt acknowledge signals.
A method for testing a multiprocessing interrupt controller, comprising:
- providing one of a plurality of processors as a master test processor;
- using said master test processor to initiate and control testing of the multiprocessing interrupt controller;
- and
- simulating a multiprocessing environment using said master test processor.
A computer system, comprising:
- a central interrupt control unit configured to process a plurality of interrupt signals;
- a plurality of I/O devices coupled to said central interrupt control unit and configured to assert said plurality of interrupt signals at said central interrupt control unit;
- and
- a processor coupled to said central interrupt control unit and configured to receive said plurality of interrupt signals from said central interrupt control unit, wherein said processor is configured to initiate a test mode for testing said central interrupt control unit, wherein in said test mode said processor is configured to emulate the operation of a plurality of processors.
A testing system comprising:
- a test processor;
- a central interrupt control unit including (a) a plurality of interrupt input channels for receiving interrupt stimulus signals, and (b) a plurality of processor interrupt channels for asserting processor interrupt signals to a corresponding plurality of processors including said test processor, wherein said central interrupt control unit controls the assertion of said processor interrupt signals based on said interrupt stimulus signals;
- wherein said test processor is coupled to each of said processor interrupt channels;
- wherein said test processor is configured (a) to initiate said stimulus signals to said interrupt input channels, (b) to receive said processor interrupt signals from said plurality of processor interrupt channels, and (c) to determine if said central interrupt control unit processed said interrupt stimulus signals correctly.
Dependencies are inferred from the claim text.