Configuration pin emulation circuit for a field programmable gate array

An integrated circuit including a circuit for emulating the inputs and outputs of a field programmable gate array (FPGA), said FPGA having a programmable stage that is initiated during Power-up and an operational stage that is initiated after the programmable stage, wherein the programmable stage of the FPGA includes an initialization state and a configuration state, said circuit for emulating comprising:

• a) counter means, activated when power is supplied to the circuit for emulating, for counting for a predetermined period of time, said counter means generating a signal when the end of said predetermined time period is reached, said counter means further comprising a power-on-reset circuit and a configuration clock counter circuit, said power-on-reset circuit including a first counter for counting to a first predetermined count, said first predetermined count generally corresponding to the period of time said FPGA is in its initialization state, and a means for generating a first command signal when said first counter reaches said first predetermined count, said configuration clock counter circuit including a second counter for counting to a second predetermined count, said second predetermined count generally corresponding to the period of time said FPGA is in its configuration state, and a means for generating a second command signal when said second counter reaches said second predetermined count;
• and
• b) pin emulation means in communication with said counter means for generating output signals that simulate the programmable stage signals occurring at the FPGA's outputs during the time said counter means is counting, and for receiving input signals and generating responsive output signals that simulate the operational stage signals occurring at the FPGAs outputs after said counter reaches said predetermined time, said pin emulation means detecting said first command signal and generating an initialization done signal in response thereto, and detecting said second command signal and generating a configuration done signal in response thereto.

A circuit for emulating the configuration pin inputs and outputs of a field programmable gate array (FPGA), said FPGA having an initialization state and a configuration state, said FPGA producing output signals to indicate to circuits external to the FPGA the present state of the FPGA, said circuit for emulating comprising:

• a) a power-on-reset circuit for counting to a first predetermined count, said first predetermined count generally corresponding to a period of time said FPGA is in its initialization state, said power-on-reset circuit being activated when power is supplied to the circuit for emulating;
• b) a configuration clock counter circuit for counting to a second predetermined count, said second predetermined count generally corresponding to a period of time said FPGA is in its configuration state;
• and
• c) pin emulation means that communicates with said power-on-reset circuit and said configuration clock counter circuit for providing FPGA initialization-mimicking output signals to the external circuits when the power-on-reset circuit is counting to the first predetermined, and for providing FPGA configuration-mimicking output signals to the external circuits when the configuration clock counter circuit is counting to the second predetermined count.

A circuit for emulating an Optimizable Reconfigurable Cell Array (ORCA) field programmable gate array (FPGA), said FPGA having a programmable stage that is initiated during power-up and an operational stage that is initiated after the programmable stage, said programmable stage having an initialization state, a configuration state, a start-up state and a reconfiguration state, said emulation circuit comprising:

• a power-on-reset circuit for counting to a first predetermined count, said first predetermined count generally corresponding to a period of time said FPGA is in its initialization state, said power-on-reset circuit including means for generating a first command signal when said power-on-reset circuit reaches said first predetermined count, said power-on-reset circuit being activated when power is supplied to the circuit for emulating;
• a configuration clock counter circuit for counting to a second predetermined count, said second predetermined count generally corresponding to a period of time said FPGA is in its configuration state, said configuration clock counter circuit including means for generating a second command signal when said configuration clock counter circuit reaches said second predetermined count;
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• a pin emulation circuit for detecting said first and second command signals, for providing FPGA initialization-mimicking output signals to external circuits until the pin emulation circuit detects the first command signal, and for providing FPGA configuration-mimicking output signals to external circuits until the pin emulation circuit detects the second command signal.

A method of emulating the configuration pin inputs and outputs of a field programmable gate array (FPGA), said FPGA having an initialization state and a configuration state, said FPGA producing output signals to indicate to circuits external to the FPGA the present state of the FPGA, said method comprising the steps of:

• a) activating a power-on-reset circuit during initial power up;
• b) counting to a first predetermined count with said power-on-reset circuit, said first predetermined count generally corresponding to a period of time said FPGA is in its initialization state;
• c) activating a configuration clock counter circuit with a signal from said power-on-reset circuit;
• d) counting to a second predetermined count with said configuration clock counter circuit, said second predetermined count generally corresponding to a period of time said FPGA is in its configuration state;
• and
• c) generating initialization-mimicking output signals during the period of time said power-on-reset circuit counts;
• and
• d) generating configuration-mimicking output signals during the period of time said configuration clock counter circuit counts.