Method and apparatus for reducing the apparent read latency when connecting busses with fixed read reply timeouts to CPUs with write-back caches

An I/O bridge comprising:

• a timer;
• means for interfacing said I/O bridge to a first bus having a first read latency timeout period;
• control logic coupled to said timer, said control logic used to control data transfers through said I/O bridge;
• and
• cycle decode logic having inputs coupled to said means for interfacing and including:
• means, responsive to a read transaction from said interfacing means, for initiating a write transaction to said interfacing means;
• and wherein said control logic further includes:
• means responsive to a write transaction from said cycle decode logic for starting said timer and for sending said read transaction after said timer has expired.

A computer system comprising:

• a processor bus;
• at least one CPU module coupled to said processor bus;
• a peripheral bus;
• an I/O adapter coupled between said processor bus and said peripheral bus;
• a first I/O bus bridge coupling a first I/O bus having a first read latency timeout period to said peripheral bus;
• a second I/O bus bridge for coupling a second I/O bus having a second read latency timeout period which is longer than said first read latency timeout period, said second I/O bus bridge coupling said second I/O bus and said peripheral bus, said second I/O bus bridge comprising:
• a timer;
• means for interfacing said second I/O bus bridge to said second I/O bus;
• control logic coupled to said timer, said control logic for regulating data transfers through said second I/O bus bridge;
• and
• cycle decode logic having inputs coupled to said means for interfacing and including:
• means, responsive to a read transaction provided from said means for interfacing to a first I/O bus, for initiating a write transaction to said means for interfacing to said second I/O bus;
• and
• said control logic further including:
• means, responsive to the write transaction from said cycle decode logic, for starting said timer and for sending said read transaction after said timer has expired.