Method and apparatus for overriding bus prioritization scheme
AssigneeTelxon Corporation
InventorBrian D. Logsdon
Life of this patent
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AssigneeTelxon Corporation
InventorBrian D. Logsdon
Estimating the term…
A bus arbiter circuit for a system including a bus and a plurality of devices which can request access to the bus at various times. The bus arbiter circuit includes circuitry for receiving requests for access to the bus from those of the plurality of devices desiring access to the bus during an arbitration cycle; circuitry for arbitrating access to the bus during the arbitration cycle in response to the received requests, an outcome of the arbitration cycle being based on a corresponding priority level associated with each of the plurality of devices; circuitry for granting access to one of those devices requesting access to the bus based on the outcome of the arbitration cycle; and circuitry for increasing the corresponding priority level associated with those of the plurality of devices which requested access to the bus but which were not granted access to the bus as a result of the arbitration cycle.
A bus arbiter circuit for a system including a bus and a plurality of devices which can request access to the bus at various times, each of the devices being configured to provide a bus request signal to the bus arbiter circuit when requesting access to the bus and to receive a bus grant signal from the bus arbiter circuit when granted access to the bus, the bus arbiter circuit comprising:
A bus arbiter circuit for a system including a bus and a plurality of devices which can request access to the bus at various times, the bus arbiter circuit comprising:
A method of bus arbitration in a system including a bus and a plurality of devices which can request access to the bus at various times, the method comprising the steps of:
A bus arbiter circuit for a system including a bus and a plurality of devices which can request access to the bus at various times, each of the devices being configured to provide a bus request signal to the bus arbiter circuit when requesting access to the bus and to receive a bus grant signal from the bus arbiter circuit when granted access to the bus, and at least one of the devices being configured to provide a hardware panic signal to the bus arbiter circuit indicative of the at least one device desiring increased priority, the bus arbiter circuit comprising:
A method of bus arbitration in a system including a bus and a plurality of devices which can request access to the bus at various times, the method comprising the steps of:
Dependencies are inferred from the claim text.