Secondary channel for communication networks

An error protection encoder, comprising:

• a processor arranged to receive a primary signal;
• a first logic device connected to receive said primary signal from said processor, said first logic device operating to generate and append parity bits;
• a second logic device connected to receive a secondary data signal from said processor, said second logic device operable to select and output a mask based upon said secondary data signal;
• and
• a logic circuit coupled to receive an output of said first and second logic device, said logic circuit operable to combine said first and second outputs received from said first and second logic devices, to produce a data frame.

An error protection decoder, comprising:

• a CPU operable to receive a frame of data;
• a first logic device operable to receive a control signal from said CPU, and to select and output a mask associated with said control signal;
• a logic circuit operable to receive said frame of data from said CPU and to combine an input signal from said CPU and the selected mask from said first logic device and produce a combined output;
• and
• a second logic device operable to receive said output of said logic circuit and calculate parity bits for comparing with received parity bits of the combined output, said second logic device further operable to transmit a signal to said CPU indicating whether said calculated and received parity bits match.

A method for transmitting information from a first logical channel and a second logical channel on one physical channel, comprising the steps of:

• error encoding a first data signal associated with the first logical channel;
• selecting a mask defining a second data signal associated with the second logical channel;
• combining the error encoded first data signal with said mask to form a combined signal;
• transmitting and receiving said combined signal;
• combining a mask having a second data signal associated therewith from a plurality of masks with said received signal to form a multiply-combined signal;
• detecting whether a violation of an error control code is present within the multiply-combined signal;
• outputting the second data signal associated with said mask used to form said multiply-combined signal and the multiply-combined signal as the first data signal, if no violation has been detected.

An error protection decoder for processing a received frame of data, comprising:

• a CPU for receiving a frame of data, said frame of data including a first data signal and a second data signal;
• a first logic device responsive to a control signal from the CPU for selecting one of a plurality of masks, each of the plurality of masks associated with a particular piece of data;
• a logic circuit for combing the received frame of data from the CPU with the selected mask to produce a combined signal;
• and
• a second logic device for calculating parity bits for the combined signal and for comparing the calculated parity bits with parity bits included with the combined signal to determine if the match;
• and
• processing means responsive to a matching determination by the second logic device for outputting the combined signal as a first data signal and for computing a second data signal associated with the selected mask.