Variable bit width cache memory architecture

In a computer system having a processor and a cache memory, wherein the cache memory includes a processor-cache interface and a plurality of cache lines, wherein each cache line includes a plurality of data words, wherein the processor and the processor-cache interface are connected by an M-word wide data bus, wherein M is greater than two, a method of transferring, from the cache memory to the processor, a single cache line from the plurality of cache lines, the method comprising the steps of:

• transferring a first group of M words in a first cache transfer cycle, wherein the first group, of M words includes a cache tag word and M-1 words from the plurality of data words, wherein the step of transferring the first group of M words includes determining an optimal transfer order for the transfer of cache line data words;
• transferring a second group of M words in a second cache, transfer cycles wherein the second group of M words includes M additional words from the plurality of data words;
• and
• transferring a third group of M words in a third cache transfer cycle, wherein the third group of M words includes M additional words from the plurality of data words.

A cache memory, comprising:

• a cache memory array having a plurality of cache lines, wherein each cache line includes a tag word and a plurality of data words;
• a processor-cache interface, wherein the processor cache interface includes an M-word wide bus, wherein M is greater than two;
• and
• a routing circuit connected to the memory array and the processor-cache interface bus, wherein the routing circuit includes first cycle transfer means for transferring a first group of M words in a first cache transfer cycle, wherein the first group includes a cache tag word and M-1 words from the plurality of data words, second cycle transfer means for transferring a second group of M words in a second cache transfer cycle, third cycle transfer means for transferring a third group of M words in a third cache transfer cycle and selection control logic, wherein the selection control logic selects an optimal set of data words to be transferred during the first cache transfer cycle.

A cache memory, comprising:

• a cache memory array having a plurality of cache lines wherein each cache line includes a tag word and a plurality of data words, wherein the plurality of words in each cache line includes an error correcting code word;
• a processor-cache interface, wherein file processor cache interface includes an M-word wide bus, wherein M is greater than two;
• and
• a routing circuit connected to the memory array ad the processor-cache interface bus, wherein the routing circuit includes first cycle transfer means for transferring a first group of M words in a first cache transfer cycle, wherein the first group includes a cache tag word and M-1 words from the plurality of data words, second cycle transfer means for transferring a second group of M words in a second cache transfer cycle and third cycle transfer means for transferring a third group of M words in a third cache transfer cycle;
• wherein the M-1 words transferred in the first cache transfer cycle include the error correcting code word for that cache line.

A computer system, comprising:

• a processor having an address bus and an M-word wide data bus, wherein M is greater than two;
• a memory connected to the processor by the address bus and the data bus;
• and
• a cache memory, wherein the cache memory includes:
• a memory array having a plurality of cache lines, wherein each cache line includes a tag word and a plurality of data words;
• a processor-cache interface connected to the processor and the memory by the address bus and the data bus;
• and
• a routing circuit connected to the memory array and the processor cache interface bus, wherein the routing circuit includes first cycle transfer means for transferring a first group of M words in a first cache transfer cycle, wherein the first group includes a cache tag word and M-1 words from the plurality of data words, second cycle transfer means for transferring a second group of M words in a second cache transfer cycle, and third cycle transfer means for transferring a third group of M words in a third cache transfer cycle
• wherein the routing circuit further includes selection control logic, wherein the selection control logic selects an optimal set of data words to be transferred during the first cache transfer cycle.