Hierarchically managed boundary-scan testable module and method

A module, said module being a hierarchically managed testable module, for use in connection with boundary-scan testing, said module comprising:

• a test-access-port (TAP) controller;
• an external boundary-scan register coupled to said TAP controller;
• and
• a plurality of internal boundary-scan registers, each of said plurality including an internal boundary-scan register coupled to said TAP controller and to said external boundary-scan register to permit data to be scanned through said external boundary-scan register without requiring data to be scanned through said internal boundary-scan register;
• said internal boundary-scan register and said external boundary-scan register each have master portions and slave portions;
• said master portions of said internal boundary-scan register and said external boundary-scan register and said TAP controller reside on a master component;
• and
• said slave portions of said internal boundary-scan register and said external boundary-scan register reside on a slave component, said master and slave components being physically separated semiconductor die electrically interconnected by conductive traces.

A method of performing hierarchically managed boundary-scan testing on an electronic module comprising steps of:

• detecting boundary-scan states at a master component;
• decoding boundary-scan instructions at said master component;
• providing a master boundary-scan register at said master component;
• providing a plurality of slave boundary-scan registers, each of said plurality including a slave boundary-scan register at a corresponding slave component;
• and
• controlling said master and slave boundary-scan registers in response to states and instructions detected and decoded, respectively, at said matter component;
• partitioning said master boundary-scan register into a master external register and a master internal register;
• partitioning said slave boundary-scan register into a slave external register and a slave internal register;
• and
• controlling said master external register, said master internal register, said slave external register and said slave internal register to permit data to be scanned through said master external register and said slave external register without requiring said data to be scanned through said master internal register or said slave internal register.

In a system comprising a plurality of boundary scan modules, a method for reducing power consumption and chip area associated with boundary scan testing, said method comprising steps of:

• providing a master component having a test-access-port (TAP) controller and having a master component boundary-scan register coupled to and controlled by said TAP controller;
• providing a plurality of slave components, each of said plurality including a slave component having a slave component boundary-scan register coupled to and controlled by said TAP controller of said master component, wherein said master and slave components are physically separated semiconductor die electrically interconnected by conductive traces;
• providing a master component includes a step of providing a master component additionally having a TDI input (test-data-in input) and a TDO output (test-data-out output), said TDI input being coupled to said master component boundary-scan register and said TDI input and TDO output being accessible from outside said module, and wherein said master component additionally has a master component internal serial data output coupled to said master component boundary-scan register and has a master component internal serial data input coupled to said TDO output;
• and
• providing a slave component includes a step of providing a slave component having an internal serial data input coupled to said master component internal serial data output and to said slave component boundary-scan register and wherein said slave component additionally has an internal serial data output coupled to said slave component boundary-scan register and to said master component internal serial data input.