Array self-test fault tolerant programmable threshold algorithm

A programmable fault tolerance apparatus which executes a built-in self-test operation on a logic array circuit, wherein the logic array circuit has a number of memory storage devices, comprising:

• a. a built-in self-test engine coupled to each of the number of memory storage devices on the logic array circuit, the built-in self-test engine for testing each of the number of memory storage devices to determine if one or more faults exist therein;
• b. a scratchpad memory storage device coupled to said built-in self-test engine for storing a location for each of the faults that are detected by the built-in self-test engine;
• c. an error counter coupled to said scratchpad memory storage device for storing a total error count of said one or more faults detected after testing the number of memory storage devices;
• d. a fault tolerance register for storing a fault tolerance number;
• and
• e. a comparator coupled to said error counter and to said fault tolerance register to compare said total error count to said fault tolerance number after testing the number of memory storage devices, the logic array circuit being valid if the magnitude of said total error count has a predetermined relationship with said fault tolerance number.

A method of executing a built-in self-test operation on a circuit design having a number of memory elements therein, the method comprising the steps of:

• a. providing a built-in self-test engine coupled to selected ones of the number of memory elements;
• b. testing each of the selected ones of the number of memory elements using the built-in self-test engine;
• c. identifying if any defects are present in the selected ones of the number of memory elements, and the locations of the defects;
• d. storing the locations of more than one of the defects identified by the built-in self-test engine;
• e. storing a fault tolerance number;
• f. storing a total defect count of said more than one of the defects identified after testing the selected ones of the number of memory elements;
• and
• g. comparing said total defect count to said fault tolerance number after testing the number of memory elements, the number of memory elements being valid if a magnitude of said total defect count has a predetermined relationship with said fault tolerance number.

A method of executing a built-in self-test operation on a logic array circuit having a number of memory storage devices, comprising the steps of:

• a providing a built-in self-test engine to test the number of memory storage devices to determine if a number of faults exist;
• b. providing a scratchpad memory storage device for storing a result of testing the number of memory storage devices on the logic array circuit if said number of faults are detected;
• c. providing an error counter for storing a total error count of said number of faults detected after testing the number of memory storage devices, said error counter updating said error count each time a particular one of the number of memory storage devices on the logic array circuit is tested when said number of faults are detected, said total error count being the total number of faults detected after testing the number of memory storage devices;
• d. providing a fault tolerance register for scanning in a fault tolerance number;
• e. providing a comparator to compare said total error count to said fault tolerance number after testing the number of memory storage devices, the logic array circuit being valid if the magnitude of said total error count is equal to or less than the magnitude of said fault tolerance number;
• f. scanning in said fault tolerance number;
• g. resetting the scratchpad memory storage device;
• h. testing said particular one of the number of memory storage devices to determine if said number of faults exist;
• i. storing a result of testing said particular one of the number of memory storage devices in the scratchpad memory storage device if said number of faults are detected;
• j. updating said error count in said error counter if said number of faults are detected;
• k. going to step (h) if all said particular ones of the number of memory storage devices have not been tested to test the next said particular one of the number of memory storage devices;
• and
• l. comparing said total error count to said fault tolerance number after testing the number of memory storage devices, the logic array circuit being valid if the magnitude of said total error count is equal to or less than the magnitude of said fault tolerance number.

A programmable fault tolerance apparatus to execute a built-in self-test operation on a logic array circuit having a number of memory storage devices, comprising:

• a. a number of built-in self-test engines wherein each particular one of said number of built-in self-test engines is coupled to a corresponding particular one of the number of memory storage devices on the logic array circuit so that each particular one of said number of built-in self-test engines can test said corresponding particular one of the number of memory storage devices to determine if a number of faults exist;
• b. a number of fault address storage registers wherein each particular one of said number of fault address storage registers is coupled to said corresponding particular one of said number of built-in self-test engines to hold a number of fault addresses, each particular one of said number of fault addresses indicating a particular one of a number of memory storage locations within said corresponding particular one of said number of memory storage devices containing a detected fault;
• c. a number of fault indicators wherein each particular one of said number of fault indicators is coupled to said corresponding particular one of said number of built-in self-test engines to indicate if said fault has been detected within said corresponding particular one of said number of memory storage devices;
• and
• d. a number of fault tolerance enable registers wherein each particular one of said number of fault tolerance enable registers is coupled to said corresponding particular one of said number of built-in self-test engines, said corresponding particular one of said number of fault tolerance enable registers being set enabling said corresponding particular one of said number of built-in self-test engines to test said corresponding particular one of the number of memory storage devices, said corresponding particular one of said number of fault tolerance enable registers not being set disabling said corresponding particular one of said number of built-in self-test engines from testing said corresponding particular one of the number of memory storage devices;
• and
• e. a test failure indicator coupled to said number of built-in self-test engines to indicate that said number of faults exists in said corresponding particular one of the number of memory storage devices if said corresponding particular one of said number of fault tolerance enable registers is set and said particular one of said number of built-in self-test engines has determined said number of faults exist in said corresponding particular one of the number of memory storage devices, said test failure indicator reading the contents of said number of fault address storage registers to uniquely identify all of said number of memory storage locations within all of the number of memory storage devices containing detected faults.

A method of executing a built-in self-test operation on a logic array circuit having a number of memory storage devices, comprising the steps of:

• a. providing a number of built-in self-test engines to test a corresponding particular one of the number of memory storage devices to determine if a number of faults exist;
• b. providing a number of fault address storage registers to hold a number of fault addresses, each particular one of said number of fault addresses indicating a particular one of a number of memory storage locations within said corresponding particular one of said number of memory storage devices contains a detected fault;
• c. providing a number of fault indicators to indicate if said number of faults has been detected within said corresponding particular one of said number of memory storage devices;
• d. providing a number of fault tolerance enable registers wherein a corresponding particular one of said number of fault tolerance enable registers being set enables said corresponding particular one of said number of built-in self-test engines to test said corresponding particular one of the number of memory storage devices, said corresponding particular one of said number of fault tolerance enable registers not being set disabling said corresponding particular one of said number of built-in self-test engines from testing said corresponding particular one of the number of memory storage devices;
• e. providing a test failure indicator to indicate that said number of faults exists in said corresponding particular one of the number of memory storage devices if said corresponding particular one of said number of fault tolerance enable registers is set and said particular one of said number of built-in self-test engines has determined said number of faults exist in said corresponding particular one of the number of memory storage devices, said test failure indicator reading the contents of said number of fault address storage registers to uniquely identify all of said number of memory storage locations within all of the number of memory storage devices containing detected faults;
• f. going to step (k) if said corresponding particular one of said number of fault tolerance enable registers is not set;
• g. testing said corresponding particular one of the number of memory storage devices with said corresponding number of built-in self-test engines to determine if said number of faults exist;
• h. going to step (k) if said corresponding number of built-in self-test engines determines said number of faults does not exist in said corresponding particular one of the number of memory storage devices;
• i. storing said number of fault addresses, each said particular one of said number of fault addresses corresponding to said particular one of said number of memory storage locations within said corresponding particular one of said number of memory storage devices where said fault has been detected;
• j. indicating that said number of faults has been detected within said corresponding particular one of said number of memory storage devices;
• and
• k. going to step (f) if all said corresponding particular ones of the number of memory storage devices have not been tested to test the next said corresponding particular one of the number of memory storage devices.