Process of testing memory parts and equipment for conducting the testing

A process of testing memory parts in a test machine having test receivers, the process comprising:

• A. providing memory parts, each memory part having binary multiples of data I/O leads, having a regular operating mode, in which all of the data I/O leads are active, and having a design for test mode, in which a certain number of the data I/O leads are active and the certain number is less than all of the data I/O leads;
• B. inserting a binary multiple of the memory parts into a test fixture;
• C. selectively connecting the certain number of data I/O leads of all the memory parts inserted in the test fixture to the test receivers by selectively opening and closing electrical connections between the data I/O leads and the receivers with relays;
• D. testing at the same time all the binary multiple of memory parts inserted in the test fixture in the design for test mode;
• E. selectively connecting all the data I/O leads of individual ones of the binary multiple of memory parts inserted in the test fixture, one memory part at a time, to the test receivers by selectively opening and closing electrical connections between the data I/O leads and the receivers with relays;
• and
• E. testing individual ones of the binary multiples of memory parts inserted in the text fixture in the regular operating mode.

A test performance board assembly for testing memory parts, each memory part having binary multiples of data I/O leads, having a regular operating mode, in which all of the data I/O leads are active, and having a design for test mode, in which a certain number of the data I/O leads are active and the certain number is less than all of the data I/O leads, the test performance board assembly comprising:

• A. a substrate;
• B. a binary multiple of memory part sockets carried on the substrate and having leads corresponding to the data I/O leads of the memory parts;
• C. plural terminals formed on the substrate;
• and
• D. a binary multiple of relays carried on the substrate and connected between the leads of the sockets and the terminals, the relays selectively connecting the leads of the sockets to the terminals by selectively opening and closing electrical connections between the leads of the sockets and the terminals, the relays being arranged to provide one set of connections between only the certain number of data I/O leads of all the sockets and the terminals and another set of connections between all of the data I/O leads of each socket and the terminals, one socket at a time.