US 5,862,143 AGranted

Byte aligner and frame synchronizer for 622 MBIT/S high-speed data

AssigneeElectronics and Telecommunications Research Institute

InventorChung-Wook Suh

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Abstract

A byte aligner and frame synchronizer for 622 Mbit/s high speed data includes a clock divider, a data width extension circuit, a byte alignment controller, a byte alignment circuit, a pattern selector, a continuous pattern detector, a frame pulse generator, a frame sync detector, a frame sync loss detector, and frame sync error detector, and performs byte alignment very fast while also stabilizing frame synchronization by reinforcing an error correction function.

Claims13

Dependent claims

A byte aligner and frame synchronizer for 622 Mbit/s high-speed data, comprising:

clock division means generating the second clock by dividing the first clock;
data width extension means for extending eight input data into sixteen outputs clocked by said first clock;
byte alignment control means for generating a control signal for byte alignment from the 16 outputs of said data width extension means;
byte alignment means for aligning bytes with the data outputted from said data width extension means driven by the byte control signal of said byte alignment control means;
A1A1 pattern detection means for detecting two continuous A1 frame bytes from data aligned in byte by said byte alignment means;
A2A2 pattern detection means for detecting two continuous A2 frame bytes from data aligned in byte by said byte alignment means;
pattern selection means for selecting one of the output signal of said A1A1 pattern detection means and the output signal of said A2A2 pattern detection means;
continuous pattern detection means for detecting whether an A1 frame pattern consisted of twelve continuous A1 frame bytes or an A2 frame pattern consisted of twelve continuous A2 frame bytes is received, in response to one of the signals from said pattern selection means in synchronization with said second clock from said clock division means;
frame pulse generation means for detecting whether said A2 frame pattern is received in sequence to said A1 frame pattern, in response to said second clock, so as to generate a frame pulse;
frame sync detection means for detecting whether said frame pulse signal from said frame pulse generation means is received continuously twice, in response to said second clock, so as to generate a frame sync signal;
frame sync loss detection means for detecting whether said frame sync signal outputted from said frame sync detection means is not received continuously four times, in response to said second clock, so as to output a frame sync loss detection signal;
and frame sync error detection means for detecting whether said frame sync loss detection signal outputted from said frame sync loss detection means is maintained for 3 msec, in response to said second clock.

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Dependencies are inferred from the claim text.

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Abstract

A byte aligner and frame synchronizer for 622 Mbit/s high-speed data, comprising:

clock division means generating the second clock by dividing the first clock;
data width extension means for extending eight input data into sixteen outputs clocked by said first clock;
byte alignment control means for generating a control signal for byte alignment from the 16 outputs of said data width extension means;
byte alignment means for aligning bytes with the data outputted from said data width extension means driven by the byte control signal of said byte alignment control means;
A1A1 pattern detection means for detecting two continuous A1 frame bytes from data aligned in byte by said byte alignment means;
A2A2 pattern detection means for detecting two continuous A2 frame bytes from data aligned in byte by said byte alignment means;
pattern selection means for selecting one of the output signal of said A1A1 pattern detection means and the output signal of said A2A2 pattern detection means;
continuous pattern detection means for detecting whether an A1 frame pattern consisted of twelve continuous A1 frame bytes or an A2 frame pattern consisted of twelve continuous A2 frame bytes is received, in response to one of the signals from said pattern selection means in synchronization with said second clock from said clock division means;
frame pulse generation means for detecting whether said A2 frame pattern is received in sequence to said A1 frame pattern, in response to said second clock, so as to generate a frame pulse;
frame sync detection means for detecting whether said frame pulse signal from said frame pulse generation means is received continuously twice, in response to said second clock, so as to generate a frame sync signal;
frame sync loss detection means for detecting whether said frame sync signal outputted from said frame sync detection means is not received continuously four times, in response to said second clock, so as to output a frame sync loss detection signal;
and frame sync error detection means for detecting whether said frame sync loss detection signal outputted from said frame sync loss detection means is maintained for 3 msec, in response to said second clock.

9 more elements