Hybrid time-slot and sub-time-slot operation in a time-division multiplexed system

Abstract

A port circuit (108) for a time-division multiplexed (TDM) switching system (100) is designed to effect sub-time-slot operation without external support, as well as to effect conventional, time-slot operation. A clock-frequency multiplier, such as a frequency-multiplexed phase-lock loop (PLL 202), and a multiplier-driven sub-time-slot operation circuit, such as a PLL-driven finite state machine (203), are incorporated into the port circuit. The clock-frequency multiplier and the sub-time-slot operation circuit generate all the additional control signals that are necessary to define sub-time slots and to effect multiple information transfers in a single time slot. The port circuit engages in conventional time-slot transfers with conventional port circuits, whereby it is compatible therewith, and engages in sub-time-slot transfers with other sub-time-slot enabled port circuits, whereby it increases the transfer throughput of the TDM switching fabric. The sub-time-slot operation is selectively enabled and disabled on a per-time-slot basis.

Dependencies are inferred from the claim text.