Non-volatile programmable memory having a buffering capability and method of operation thereof

A memory integrated circuit responsive to externally furnished memory addresses for storing or furnishing data, comprising:

• a memory array having a plurality of non-volatile erasable-programmable memory cells selectively accessible in groups of a common size based on the memory addresses;
• a high voltage circuit coupled to the memory array;
• a first buffer having at least a number of storage positions corresponding to the size of the groups;
• and
• a second buffer having at least a number of storage positions corresponding to the size of the groups;
• wherein the first buffer is accessible externally of the memory independently of the memory array while the second buffer is accessible internally to the memory for transferring data to the memory array.

A memory integrated circuit comprising:

• a plurality of data nodes;
• a buffer having a plurality of storage positions respectively coupled to the data nodes;
• a memory array having a plurality of non-volatile erasable-programmable memory cells selectively accessible in groups, the memory cells of a selected group being respectively coupled to the storage positions of the buffer;
• and
• a high voltage circuit coupled to the memory array;
• wherein the storage positions of the buffer are loadable and readable through the data nodes independently of the memory array.