Semiconductor memory device having optimally arranged internal down-converting circuitry

A semiconductor device formed on a chip, comprising:

• a reference voltage generating circuit located in a first region of a periphery of a region where said 5 semiconductor device is located on said chip, for generating a reference voltage;
• and
• a plurality of driving circuits each located in a second region different from said first region for producing an internal power supply voltage on a corresponding internal power supply line, each of said driving circuits including
• (i) a variable level shifting circuit capable of adjusting a level shift amount of a voltage on a corresponding internal power supply line, and
• (ii) an internal voltage adjusting circuit for comparing an output voltage of said variable level shifting circuit with the reference voltage from said reference voltage generating circuit and supplying a current from an external power supply voltage application node to a corresponding internal power supply line in accordance with the comparison result;
• a tuning circuit located in said first region and coupled in common to each of said plurality of driving circuits for setting a level shift amount of each said variable level shifting circuit of said plurality of driving circuits.

A semiconductor memory device formed on a chip, comprising:

• a first region extending in a first direction and arranged on a center portion of said chip with respect to a second direction perpendicular to said first direction,
• a second region extending in the second direction and arrange on a center portion of said chip with respect to the first direction;
• said first region and said second region dividing said chip into four sub regions,
• a plurality of memory arrays each including a plurality of memory cells arranged in rows and columns, the memory arrays arranged corresponding to said four sub regions respectively;
• a plurality of control circuits provided corresponding to said plurality of memory arrays, for performing an operation related to at least column selection in corresponding memory arrays;
• a reference voltage generator provided in a periphery of said first region for generating a reference voltage at a predetermined voltage level;
• internal voltage generators provided in said second region and corresponding to the memory arrays, for receiving said reference voltage and an external voltage externally applied to convert the received external voltage into an internal voltage at the reference voltage level for application to the corresponding control circuits.