Semiconductor memory having both a refresh operation cycle and a normal operation cycle and employing an address non-multiplex system
AssigneeHitachi, Ltd.
InventorsYasushi Takahashi, Takashi Shinoda, Masamichi Ishihara, Tetsu Udagawa, Kazumasa Yanagisawa
Life of this patent
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Abstract
An ordinary read/write operation (normal operation) and a refresh operation are separated from one another and the number of read amplification circuits or in other words, the number of sense amplifiers operating during the normal operation is made smaller than that during the refresh operation. Accordingly, a bit line charge/discharge current during the normal operation can be reduced.
Claims17
A semiconductor device with a dynamic memory employing an address non-multiplex system comprising:
- a plurality of data lines arranged in parallel;
- a plurality of sense amplifiers coupled to said data lines;
- a main word line;
- a plurality of sub-word lines arranged along a straight line parallel to said main word line;
- a plurality of single-MOSFET type dynamic memory cells, each of which is arranged, with respect to a plan view of said plurality of data lines, to correspond to an intersection of one of said data lines and one of said sub-word lines;
- a plurality of gate circuits, each of which is coupled to said main word line and a corresponding sub-word line;
- and
- a plurality of selecting lines, each of which is coupled to a corresponding gate circuit,
- wherein said plurality of sub-word lines are set simultaneously in selected states in a refresh operation, and
- wherein one of said plurality of sub-word lines is set in a selected state in said normal operation.
A semiconductor device with a dynamic memory employing an address non-multiplex system comprising:
- a plurality of data lines arranged in parallel along a first direction;
- a plurality of word lines arranged in parallel along a second, perpendicular direction and intersecting, with respect to a plan view of a main surface of said device, said data lines,
- wherein each word line includes a main word line and a plurality of sub-word lines arranged along a straight line parallel to said main word line;
- a plurality of sense amplifiers coupled to said data lines, respectively;
- a plurality of single-MOSFET type dynamic memory cells, each of which is arranged to correspond to an intersection of one of said data lines and one of said sub-word lines;
- a plurality of gate circuits, each of which is coupled to a respective said main word line and a sub-word line corresponding thereto;
- and
- a plurality of selecting lines, each of which is coupled to a gate circuit coupled to each of said main word lines,
- wherein said plurality of sub-word lines are set simultaneously in selected states in a refresh operation, and
- wherein one of said plurality of sub-word lines is set in a selected state in a normal operation.
Dependencies are inferred from the claim text.