Memory accessible in read mode only
AssigneeSGS-Thomson Microelectronics S.A.
InventorsThierry Bion, Richard Ferrant
Life of this patent
Estimating the term…
Abstract
A memory accessible in read mode only comprises storage elements designed to contain a bit that can assume two levels. Each memory cell comprises a transistor. The transistor of the storage element may include an associated circuit portion to prompt a short circuit between the drain and the source of the transistor if the storage element has to contain one bit at one of the two levels. Furthermore, the use of an unbalanced differential amplifier permits an improvement of the access time of the memory.
Claims16
A memory accessible in a read mode only comprising:
- a plurality of storage elements arranged in rows and columns, each storage element for containing a bit that can assume one of two levels, and each storage element comprising
- a transistor having a drain and a source, and
- short circuit prompting means associated with the transistor for prompting a short circuit between the drain and the source of said transistor if the storage element has to contain one bit at one of the two levels;
- all the transistors of the storage elements belonging to one and the same column being series-connected;
- and
- a differential amplifier having first and second inputs internally unbalanced with respect to each other, the first input being connected to the drain of a transistor that is located at a first end of a column.
A memory accessible in a read mode only, comprising:
- a plurality of storage elements arranged in rows and columns, each storage element for containing a bit that can assume one of two levels, and each storage element comprising
- a transistor having a drain and a source, and
- short circuit prompting means associated with the transistor for prompting a short circuit between the drain and the source of said transistor if the storage element has to contain one bit at one of the two levels;
- all the transistors of the storage elements belonging to one and the same column being series-connected;
- a pre-charging transistor having a drain connected to the drain of a transistor that is located at a first end of a column;
- a reference transistor identical to the pre-charging transistor;
- and
- a differential amplifier having a first input connected to the drain of the pre-charging transistor and a second input connected to the reference transistor, the first and second inputs of said differential amplifier being internally unbalanced.
Dependencies are inferred from the claim text.