Semiconductor memory device having cell array divided into a plurality of cell blocks

A Dynamic Random Access Memory, comprising:

• a cell array divided into a plurality of cell blocks, each cell block including,
• a plurality of memory cells arranged in a matrix form, and
• a plurality of bit lines arranged to cross a plurality of word lines for transferring data to or from a selected memory cell;
• a plurality of bit line sense amplifiers respectively connected to said bit lines;
• a cell block selection circuit for selecting at least one of said plurality of cell blocks;
• a plurality of data I/O lines to which said bit lines are connected;
• a first precharge circuit connected to said data I/O lines and precharging said data I/O lines to a first potential equal to a precharge potential of said bit lines;
• a second precharge circuit connected to said data I/O lines and precharging said data I/O lines to a second potential different from the precharge potential of said bit lines;
• and
• a selective drive circuit for generating control signals to be supplied to said first and second precharge circuits to cause said first precharge circuit to precharge said data I/O lines connected to non-selected cell blocks of said cell blocks to the first potential and to cause said second precharge circuit to precharge said data I/O line connected to said at least one selected cell block to the second potential.

A Dynamic Random Access Memory comprising:

• a cell array divided into a plurality of cell blocks, each cell block including,
• a plurality of memory cells arranged in a matrix form, and
• a plurality of bit lines arranged to cross a plurality of word lines for transferring data to or from selected memory cells, said bit lines being precharged to a first potential;
• a plurality of bit line sense amplifiers respectively connected to said bit lines;
• a cell block selection circuit for selecting at least one of said plurality of cell blocks;
• a plurality of data I/O lines to which said bit lines in the at least one selected cell block selected by said cell block selection circuit are connected through respective column selection gates;
• a plurality of column selection signal lines arranged across said plurality of cell blocks, each column selection signal line commonly coupled to associated column selection gates in a same column of said plurality of cell blocks;
• and
• a selection gate control circuit provided between said column selection signal lines and said column selection gates, said selection gate control circuit precharging at least a selected data I/O line of said at least one selected cell block to a second potential and maintaining non-selected data I/O lines of non-selected cell blocks at said first potential.