Redundancy circuit for memory devices having high frequency addressing cycles
AssigneeSamsung Electronics Co., Ltd.
InventorSeung-Hun Lee
Life of this patent
Estimating the term…
Abstract
A redundancy circuit for activating redundant memory cells when a semiconductor memory device is found to have defective memory cells, which redundancy circuit comprises, in order to overcome the problems of an address reset and a precharging of the first node which determines the redundancy addressing output signal of the redundancy circuit, additional switching circuit which is controlled by a clock signal of the memory device being made to be connected between a ground node and a switching circuit connected to a plurality of fuses, and a precharging circuit for precharging the first node to a high voltage level being made to also controlled by the clock signal.
Claims38
A redundancy circuit providing a redundancy addressing signal for activating redundant memory cells in place of defective memory cells in a semiconductor memory device, said redundancy circuit comprising:
- an input node for receiving a control signal;
- a first node for determining a voltage level of the redundancy addressing signal;
- a programming means for programming repair information of the defective memory cells, the programming means being connected between the first node and a second node;
- precharging means for precharging said first node to a first voltage supply level, said precharging means being connected between said first node, a third node, and the input node, the third node for receiving a first voltage supply;
- first switching means for discharging said first node to a second voltage supply, said first switching means being connected between the second node, a fourth node, and the input node, the fourth node for receiving the second voltage supply;
- and
- transmission means connected for transferring the voltage level of said first node to a redundancy addressing signal terminal, whereby the precharging means, the first switching means, and the transmission means are responsive to the single control signal.
A redundancy circuit providing a redundancy addressing signal for activating redundant memory cells in place of defective memory cells in a semiconductor memory device, said redundancy circuit comprising:
- a first node for determining a voltage level of the redundancy addressing signal;
- precharging means for precharging said first node to a first voltage supply level responsive to an internal and a first control signal of the semiconductor memory device, said precharging means being connected to said first node and having a second node for receiving a first voltage supply;
- a plurality of fuses each connected at a first end to said first node;
- first switching means for uncoupling said first node and a fourth node responsive to a defective memory cell address signal, said first switching means being connected between the fourth node and a second end of each of said plurality of fuses;
- and
- second switching means for discharging said first node to a second voltage supply level responsive to the first control signal, said second switching means connected between the fourth node and a second voltage supply.
A method for providing a redundancy addressing signal for activating redundant memory cells in place of defective memory cells in a semiconductor memory device, the memory device having a plurality of fuses and a first and second switching circuits, the method comprising:
- precharging a first node to a voltage level responsive to a control signal;
- receiving a memory cell address to the first switching circuit, the first switching circuit having a plurality of switching elements, each of the plurality of switching elements receiving a memory cell address bit;
- connecting the first node to a redundancy address signal terminal such that the voltage level of the first node is substantially equal to a voltage level of the redundancy address signal responsive to the control signal;
- disconnecting the first node from the redundancy address signal terminal responsive to the control signal;
- and
- maintaining the voltage level of the redundancy address signal with a latching circuit.
A method for providing a redundancy address signal for replacing defective memory cells for redundant memory cells in a semiconductor memory device, the method comprising:
- generating an internal control signal responsive to a second control signal;
- precharging a first node to a first voltage supply level responsive to a first voltage level of the internal control signal and to a first control signal;
- providing a memory cell address signal for the defective memory cell to a first switching circuit;
- coupling the first node to a redundancy addressing signal node responsive to a first voltage level of the first control signal such that a voltage level of the first node is substantially equal to a voltage level of the redundancy addressing signal;
- and
- decoupling the first node from the redundancy signal node responsive to a second voltage level of the first control signal.
Dependencies are inferred from the claim text.